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MSP430FR2111: Timer B TBIV does not reset upon ISR

Eyal Lasko
Expert 2300 points
Part Number: MSP430FR2111
Other Parts Discussed in Thread: MSP430FR2311

Hi, 

I've initialized timer B in Up mode and implemented TIMER0_B1_VECTOR ISR in order to intercept timer wrap-around.

I've placed a breakpoint in the ISR and notice that every time when the breakpoint is triggered, TBR slightly increase (3/4 counts) as if TBIFG never resets and constantly triggers the ISR.

The user guide mentions that "Any access, read or write, of the TBxIV register automatically resets the highest-pending interrupt flag. " which I don't see happening...

Thanks for any advise.

  • 0
    Guru 95150 points
    The breakpoint arrow is pointing at the switch statement, so TB0IV hasn't been read yet; thus it still shows 0x0E.

    TB0R has continued to count after the ISR was entered. With ID=0 it is unremarkable that it has progressed some small amount past 0.
  • 0 in reply to Bruce McKenney
    Expert 2300 points
    Thanks Bruce for your prompt reply

    I understand your point but:
    - For some reason I can't set the breakpoint on the case statemet (optimization ?)
    - TB0R which shows 0x0007 on the screen cap, showed 0x0004 on the previous iteration and 0x000A on the next iteration, so apparently it is not a minute progress after IFG have occured but a consistent increase in value , this is why I suspected that TBIFG isn't cleared and the ISR is repeatedly triggered.
    This behavior continues until it reaches TB0CCR0 and then CCR0 ISR is triggered as expoected (TIMER0_B0_VECTOR).

    Another thought:
    As MSP430FR2111 Timer B0 has only 3 CCR modules, maybe I have to use only 3 CCRx case statement (0/2/4) and then the TBIFG (so its value is 6 instead of 14) case statement ??

    Thanks again
  • 0 in reply to Eyal Lasko
    Guru 95150 points
    1) Yes, I usually blame the optimizer for an inability to set a breakpoint where I want. The disassembly might be interesting.
    2) A small variation in TB0R (say <10 ticks) could be due to what kind of instruction was interrupted (the CPU won't interrupt in the middle of an instruction). If you're disabling interrupts elsewhere, of course, it could vary even more.
    3) My guess (without checking the Book) is that the IV values are architected for an entire product line, even if some of the CCRs aren't implemented. If you're concerned, look in msp430fr2111.h (right click on TBIV__TBIFG and "go to definition").

    You can try -O0 and/or if you have a scope try wiggling a GPIO to see the interrupt period. 60K ticks might even be long enough to see on an LED.
  • 0 in reply to Eyal Lasko
    Guru 95150 points
    Typo alert (I wasn't looking closely enough): TBIV is not the same as TB0IV. You want the latter in your switch().
  • 0 in reply to Bruce McKenney
    Expert 2300 points

    Note that my code is based on driverlib's sample "timer_b_ex2_overflowISR" (for MSP430FR2311).

    The sample code does use TBIV (and not TB0IV as you suggested).

    I'll give it a try shortly and report back.

    THANKS

  • 0 in reply to Eyal Lasko
    Guru 95150 points
    My copy of msp430fr2111.h (and 2311.h) says TBIV=(0xffff) -- i.e. a constant -- which would (presumably) cause your entire ISR to be optimized away -- thus your symptoms. If that's what that other example is doing, I don't know how it's working.
  • 0 in reply to Eyal Lasko
    Expert 2300 points

    Hey Bruce,

    You were right. TB0IV worked like a charm...

    THANKS !

  • 0 in reply to Eyal Lasko
    Guru 95150 points
    I managed to locate that example program, and when I compile it (even with -O0) the TIMERB1_ISR is empty -- just a RETI. When I find my Launchpad, I expect it to display the symptoms you were observing.

    I suspect this one slipped through the cracks somehow. Good catch.
  • 0
    TI__Genius 12315 points

    Hi ,

    I have confirmed it is a typo error in code example. We will fix it and update. Thank you for reporting. 

    If my post helped solve your issue, please click on the  VERIFY ANSWER    button. 

    Winter,

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