Hi,
I am thrying to interface external spi memory 25LC256 to MSP430 development kit.
The things that i have achieved so far is:
1)SPI INIT
2)send dummy data in spi tx buff abd recieve the same in rx buff
3)then i warite data to the memory (16 bit addr 8 bit data 0xa0).Each and every byte is echoed in rx buff
4) then i try to read mem by sending dummy data 0x00.but i dont recieve and data from memory. what i rx always is dummy data written.
My issue is how do i confirm the communication is through and data is written to SPI memory.
I follow all the instruction,steps to do write as well as read data.
I am attaching the spec and my code.Kindly let me know if anything can be done about this. or anybody has faced any similar issues.
Looking foraward for your kind support.
Thanks and Regards
Manisha
// code
//unsigned int UART_Data = 0;
UInt8 SPI_RxData = 0;
UInt8 SPI_TxData = 0;
UInt16 SPI_MemAddr = 0x0002;
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
SPI_Initialization(); // Initialize SPI
while (1)
{
__bis_SR_register(GIE); // enable interrupts
RESET_BUSY_FLAG();
UCB0TXBUF = 0x55; //WRITE DATA
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
SET_BUSY_FLAG();
while((P3IN & 0x01)); // Verifies busy flag
RESET_BUSY_FLAG (); // CS bought to low to start
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = SET_WRITE_LATCH; // latch write enable sequence
while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
SET_BUSY_FLAG(); // CS bought to hight to latch the wr instruction
__no_operation(); //one wait state
RESET_BUSY_FLAG(); // CS bought to low to start
// start write instruction
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = WRITE_INSTR; // write instr
while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
//WRITE HIGHER ADDR FIRST
UCB0TXBUF = (SPI_MemAddr & 0xff00)>>0x08;
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
UCB0TXBUF = (SPI_MemAddr & 0x00ff); // WRITE LOWER 16 BIT ADDR
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
UCB0TXBUF = 0x55; //WRITE DATA
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
__no_operation(); //wait one cycle
SET_BUSY_FLAG(); // CS bought to hight to latch the wr instruction
RESET_BUSY_FLAG();
while((P3IN & 0x01)); // Verifies busy flag
IFG2 &= ~UCB0RXIFG;
RESET_BUSY_FLAG (); // CS en
UCB0TXBUF = READ_INSTR; //Send read inst to SPI
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
UCB0TXBUF = (SPI_MemAddr & 0xff00)>>0x08; // Send 16 bit memory Higher addr
//UCB0TXBUF = (SPI_MemAddr & 0xff00); // Send 16 bit memory Higher addr
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
UCB0TXBUF = (SPI_MemAddr & 0x00ff); // Send 16 bit memory lower addr
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
UCB0TXBUF = 0x00;
while (!(IFG2 & UCB0RXIFG)); // USCI_B0 TX buffer ready?
SPI_RxData = UCB0RXBUF;
SET_BUSY_FLAG(); // CS bought to hight to latch the wr instruction
}
}
void SPI_Initialization(void)
{
//1) -> initialization/re-configuration process <-BEGIN
UCB0CTL1 |= UCSWRST;//Set UCSWRST -- needed for re-configuration process
//1) END
//2) -> Initialize all USCI registers Set <- BEGIN
// CONTROL REGISTERS
//UCB0CTL0 -> Control Register 0
// 7 | 6 | 5 | 4 | 3 | 2-1 | 0 |
//-------------------------------------------------------------------------
//UCCKPH|UCCKPL|UCMSB|UC7BIT|UCMST|UCMODEx|UCSYNC|
//UCCKPH (Clock phase) = 0b -> Data is changed on the first UCLK edge and captured on the following edge.
//UCCKPL (Clock polarity) = 0b -> The inactive state is low
//UCMSB (MSB first select) = 1b -> MSB first
//UC7BIT (Character length) = 0b -> 8-bit data
//UCMST (Master mode) = 1b -> Master mode
//UCMODEx (USCI mode) = 00b -> 3-Pin SPI
//UCSYNC (Synchronous mode enable) = 1b -> Synchronous mode
UCB0CTL0 = 0x29;
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//UCA0CTL1 -> Control Register 1
// 6-7 | 5 | 4 | 3 | 2 | 1 | 0 |
//---------------------------------------------------------
//UCSSELx | Unused |UCSWRST|
//---------------------------------------------------------
//UCSSELx (USCI clock source select)= 10b -> SMCLK
//UCSWRST (Software reset) = 1b -> normally set by a PUC
UCB0CTL1 = 0x81;
//-------------------------------------------------------------------------
// DATA RATE
// Data rate = SMCLK/2 ~= 500kHz
// UCA0BR1 = 0x00 & UCA0BR0 = 0x02
//-------------------------------------------------------------------------
UCB0BR0 = 0x02;
UCB0BR1 = 0x00;
//-------------------------------------------------------------------------
//2) END
//3) Configure ports <-BEGIN
P3SEL |= 0x0E; // P3.1,P3.2,P3.3 option select
//3) END
//4) Clear UCSWRST via software -> BEGIN
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
//4) ->END
//5) Enable interrupts -> BEGIN
// Not used
//5) -> END
// IE2 |= UCB0TXIE; // Enable USCI_A0 TX interrupt
// IE2 |= UCB0RXIE; // Enable USCI_A0 RX interrupt
}
