MSP430FR4133: multiple ADC channel sequencing reading probblem

Hi Ajay
could you please help to test FR4133 code example "msp430fr413x_adc10_10.c" firstly?
Go trough the code provided, I think the problem is (from UG) "A sequence of channels is sampled and converted once. The sequence begins with the channel selected by the ADCINCHx bits and decrements to channel A0. Each ADC result is written to ADCMEM0. The sequence stops after conversion of channel A0".

CONSEQ=1 (or =3) with MSC=1 is a challenge on the FR2/4 since there's only one result word and no DMA.

SLAU445G Figure 20-11 shows that with SHT=2 (16-clock sampling) each conversion takes (16+12+1)=29 ADC clocks. You should budget at least 30 CPU clocks to get into/out of the ISR, plus whatever you want to do there (so make a guess at 50 CPU clocks). The MODCLK is running at about 5x the CPU clock, so each conversion runs in about 5 CPU clocks.

Result: You will not succeed in grabbing the first sample before the second sample overwrites it. (Even with ADCCLK=SMCLK[1MHz] you won't succeed.) I'm not at all convinced that adc10_10 works properly either, though I haven't tried it.

Perhaps the simplest fix is to use ACLK (REFOCLK=32kHz), though this is pretty slow.

Alternatively, using SMCLK and ADCDIV=7 would give you (29*8)=232 CPU clocks to grab the sample, which should be enough if you're not doing anything else.

Keep in mind that the ADC will keep counting down through channels 6-0, interrupting each time, which (at 232 CPU clocks each) will take a while.

I was curious, so I tried example msp430fr413x_adc10_10.c, and indeed it fails -- in that case the symptom was that it never got out of LPM since the interrupts overran each other and "i" never reached 0.

For that example, using ADCSSEL_2 [SMCLK] with ADCDIV_1 [/2] was (just barely) adequate.

#include <msp430.h>

int ADC_Result[2]; // 8-bit ADC conversion result array
int i=1;
int a=0;
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT

// Configure ADC A7~8 pins
SYSCFG2 |= ADCPCTL7 | ADCPCTL8;

// Configure XT1 oscillator
P4SEL0 |= BIT1 | BIT2; // P4.2~P4.1: crystal pins

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;

FRCTL0 = FRCTLPW | NWAITS0; // Set number of FRAM waitstates to 0

CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK; // Set ACLK = XT1; MCLK = SMCLK = DCO

do
{
CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1 & OFIFG); // Test oscillator fault flag


// Configure ADC
ADCCTL0 |= ADCSHT_2 | ADCMSC | ADCON; // 16ADCclks, MSC, ADC ON
ADCCTL1 |= ADCSHP | ADCCONSEQ_3|ADCSSEL_1; // ADC clock ACLK, sampling timer, s/w trig.,Repeat-sequence-of-channels
ADCCTL2 |= ADCRES; // 10-bit conversion results
ADCMCTL0 |= ADCINCH_8 | ADCSREF_1; // A7-8(EoS); Vref=1.5V
ADCIE |= ADCIE0; // Enable ADC conv complete interrupt

// Configure reference
PMMCTL0_H = PMMPW_H; // Unlock the PMM registers
PMMCTL2 |= INTREFEN; // Enable internal reference
__delay_cycles(400); // Delay for reference settling
__no_operation();

while(ADCCTL1 & ADCBUSY); // Wait if ADC core is active
ADCCTL0 |= ADCENC | ADCSC; // Sampling and conversion start
__bis_SR_register(GIE);
while(1)
{
a++;
if(a==10000) //just for check
a=0;
}
}

// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
{
case ADCIV_NONE:
break;
case ADCIV_ADCOVIFG:
break;
case ADCIV_ADCTOVIFG:
break;
case ADCIV_ADCHIIFG:
break;
case ADCIV_ADCLOIFG:
break;
case ADCIV_ADCINIFG:
break;
case ADCIV_ADCIFG:
ADC_Result[i] = ADCMEM0;
if(i == 0)
{
i = 1;
}
else
{
i--;
}
ADCIFG = 0;
break;
default:
break;
}
}


i have check this with clock of ACLK whi 32KHz and give same result as like decimal equivalent count vary from 425,777,1023,764,722,719,764,612 ( which is any random value ) while i am expecting output count is around 342 decimal which is equivalent to 0.5V with reference of 1.5V .

Hello ,
my circuit which is basically three resistor array network ( each network can generate 0 to 1.25V with the step of 125mV) with rotary switch which control out put voltage followed by a low pass filter with cut off frequency is around 725Hz (100 ohms and 2.2UF cap) for each network..
this circuit i have tested with MSP432 launch pad (14 bit ADC) with 2 channel sequentially which give proper 1700 decimal step which is correspond to 125mV
now same board with MSP430FR4133 which give the problem as i mention in previous replies.

i have pasted two different code in my replies  

first one is of single sequence with internal clock 5MHz

and repeat sequence with ACLK of 32KHz

are they correct like TI suggestion ? or not .if not then what should i do change in the code.

does this MSP430FR4133 launchpad actually support multiple channel sequencing ? does anyone did this actually sequential channel  sampling on MSP430FR4133 launch pad ? if yes please suggest what changes i should to work in sequential sequences sampling.  

> Keep in mind that the ADC will keep counting down through channels 6-0, interrupting each time,
Your indexing scheme is storing the results from channels 6-0 over the ones from 8-7. The simplest change here is probably to expand ADC_Result[] to 9 entries to store them all, then ignore the first 7.

* does anyone did this actually sequential channel sampling on MSP430FR4133 launch pad ?
Per my previous response: I did this just last night. I didn't use CONSEQ=3 since you asked about CONSEQ=1, but the principle is pretty much the same.

Unsolicited:
> ADCIFG = 0;
I recommend that you not do this, since reading ADCMEM0 clears ADCIFG0. It may not be causing trouble now, but it will eventually.

I don't have my materials here, but I suppose that this:

> For that example, using ADCSSEL_2 [SMCLK] with ADCDIV_1 [/2] was (just barely) adequate.

[see also SLAU445G Table 20-4] means I changed line 89 of msp430fr413x_adc10_10.c [SLAC625E] from this:

> ADCCTL1 |= ADCSHP | ADCCONSEQ_1; // ADC clock MODCLK, sampling timer, s/w trig.,single sequence

to this:

> ADCCTL1 |= ADCSHP | ADCCONSEQ_1|ADCSSEL_2|ADCDIV_1; // SMCLK/2, sampling timer, s/w trig.,single sequence

Did you try something like this? How about the other changes I suggested?