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MSP430FR5969: How many capture compare modules are there on the ta0 instance of Timer A?

Part Number: MSP430FR5969

Hi, 

If you take a look at SLAS704F you will notice that in the Functional Block Diagram it mentions that there are 3 capture/compare modules attached to the ta0 instance of Timer A. But if you look at the Peripheral File Map in section 6.10.20 in the same document there are base addresses for five capture compare modules?

I am a little confused by this documentation, can someone clear it up?

Thanks

  • basically I need to know: Is it five or three capture compare modules on the ta0 instance of Timer A?
  • Also, please point me to any documentation that may offer an answer.
  • Hi Jennifer,

    the basic document for your MSP430 family is

    It says that Timer_A can have up to 7 CC registers:

    For a MSP430FR5969 TI provides an example project msp430fr59xx_ta0_01.c
    The core project file msp430fr59xx_ta0_01.c contains main() and includes the include statement:

    #include <msp430.h>

    This statement includes:

    #elif defined (__MSP430FR5969__)
    #include "msp430fr5969.h"

    In the msp430fr5969.h, beginning from line 3375, you will find :

    SFR_16BIT(TA0CTL);                            /* Timer0_A3 Control */
    SFR_16BIT(TA0CCTL0);                          /* Timer0_A3 Capture/Compare Control 0 */
    SFR_16BIT(TA0CCTL1);                          /* Timer0_A3 Capture/Compare Control 1 */
    SFR_16BIT(TA0CCTL2);                          /* Timer0_A3 Capture/Compare Control 2 */
    SFR_16BIT(TA0R);                              /* Timer0_A3 */
    SFR_16BIT(TA0CCR0);                           /* Timer0_A3 Capture/Compare 0 */
    SFR_16BIT(TA0CCR1);                           /* Timer0_A3 Capture/Compare 1 */
    SFR_16BIT(TA0CCR2);                           /* Timer0_A3 Capture/Compare 2 */
    SFR_16BIT(TA0IV);                             /* Timer0_A3 Interrupt Vector Word */
    SFR_16BIT(TA0EX0);                            /* Timer0_A3 Expansion Register 0 */

    Jennifer,

    it is always better to deal with a real software than a time to time documentation fakes.
    Go with 3 CC registers.

    Congratulations for your careful readings!

    I will post the detailed remarks to the documents.
    Now, it is past 2 a.m. my time.

    Cheers!

  • Hello there !

    TA0_3 in the FR5969 has 3 CCR's

    Here's another way to look at it - how TI names the Timer A in an MSP430. For example, the TA0_3 on the 5969 :


    TA - the timer type (there is also a Timer B type)

    0 - the first timer of this type (the 5969 has TA_0 , 1 , 2, 3. So, 4 TA types))

    _3 - this means 3 CCR instantiations (on the 5969, TA2_2 and TA3_2 have 2 CCRs)


    And this seems to be consistent across TI's documentation.

    Cheers!
  • Hello Otto,

    document name: http://www.ti.com/lit/ds/symlink/msp430fr5969.pdf

    with an annotation on page headers:

    SLAS704F–OCTOBER 2012–REVISED MARCH 2017

    on page #76 says:

    Why do you say that this particular TA0 has 3 CCRs?

    It does not seem to be consistent across the documentation.

  • Well spotted Tomasz,

    Here's what I just pulled out of the same data sheet you referenced:

    6.10.10 TA0, TA1
    TA0 and TA1 are 16-bit timers and counters (Timer_A type) with three capture/compare registers each. TA0 and TA can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-13 and Table 6-14). TA0 and TA have extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.


    Also, the block diagram shows TA0_3 (and TA1, TA2, TA3):

    1.4 Functional Block Diagram
    Figure 1-1 shows the functional block diagram of the devices

    So, you're right, there is something strange about the document. Totally agreed.

    If I really wanted to dig further (I won't though), I would just boot up CCS, write a small program which tries to access all the CCRs from 0 to say 7. Then see where the compiler flags the error. Crude but fast.

    I have several MSP's here but not a 5969.


    I can understand the original question now !

    cheers,
  • Yes the problem with the documentation that I originally mentioned, Tomaz provided screenshots for. 

    I find it **VERY** problematic that I have to dig through code because the documentation isn't consistent across all sources. Documentation should be the main source of understanding the processor and the example code **NOT** the other way around. 

    It would be great if someone from TI could clear this up.

  • It is better (and also standard practice) to deal with documentation and not code.
  • Otto, I understand the instantiations, I am asking about inconsistencies across documentation
  • Jennifer,

    I have submitted a documentation feedback to TI team.

    I see 3 options for you:
    1) other MCU if you really need 5 CCRs for TA0, 5994 has 7 CCRs for TA0 as I remeber
    2) do what you need with 3 CCRs
    3) quick test may help. Add TA0CCTL3 and TA0CCTL4 to msp430fr5969.h and write a simple test code. After reset TA0CCTL9-2 register should contain 0x0000. What would you gain from TA0CCTL3-4? 0x0000, 0xFFFF or ISR?

  • Hi Jennifer,
    I indeed understand your point. Let's hope TI steps up and addresses it to your satisfaction.
    Cheers,,,,
  • .... of course Jennifer hasn't given the technical requirements, just the comments on documentation.
    But giving 'free advice' is hard to resist, so ..... if they need more CCR's in a 5969, why not just use the Timer B as it has 7.
  • Jennifer,

    I did the test.

    #include <stdint.h>
    #include "driverlib.h"
    
    static uint16_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
    
    int main(void) {
    
        WDT_A_hold(WDT_A_BASE);
    
        HWREG16(TIMER_A0_BASE + OFS_TAxCCR0) = 100;
        HWREG16(TIMER_A0_BASE + OFS_TAxCCR1) = 1;
        HWREG16(TIMER_A0_BASE + OFS_TAxCCR2) = 2;
        HWREG16(TIMER_A0_BASE + OFS_TAxCCR3) = 3;
        HWREG16(TIMER_A0_BASE + OFS_TAxCCR4) = 4;
    
        ccr0 = HWREG16(TIMER_A0_BASE + OFS_TAxCCR0);
        ccr1 = HWREG16(TIMER_A0_BASE + OFS_TAxCCR1);
        ccr2 = HWREG16(TIMER_A0_BASE + OFS_TAxCCR2);
        ccr3 = HWREG16(TIMER_A0_BASE + OFS_TAxCCR3);
        ccr4 = HWREG16(TIMER_A0_BASE + OFS_TAxCCR4);
    
        ccr0 += ccr1 + ccr2 + ccr3 + ccr4 + ccr5 + ccr6;
    
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR0) = 100;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR1) = 1;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR2) = 2;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR3) = 3;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR4) = 4;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR5) = 5;
        HWREG16(TIMER_B0_BASE + OFS_TBxCCR6) = 6;
    
        ccr0 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR0);
        ccr1 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR1);
        ccr2 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR2);
        ccr3 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR3);
        ccr4 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR4);
        ccr5 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR5);
        ccr6 = HWREG16(TIMER_B0_BASE + OFS_TBxCCR6);
    
        ccr0 += ccr1 + ccr2 + ccr3 + ccr4 + ccr5 + ccr6;
    
        return (0);
    }
    

    TA0 and TA1 have 3 CCRs.

    TA2 and TA3 have 2 CCRs

    TB0 has 7 CCRs.

    In case of TA0 you can write to CCR3 and CCR4 without errors.
    When you read these registers you receive 0x0000.

    Please mark this post as resolved.

  • Thank you Tomasz for the help!

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