MSP432P401R: Clock gating

Ronny Landsverk

Part Number: MSP432P401R
Other Parts Discussed in Thread: TM4C123GH6PM

Regarding the Tiva TM4C123GH6PM Launchpad, you can enable and provide a clock to GPIO "blocks" using the RCGCGPIO register.

For the MSP432P401R SimpleLink Launchpad, is there some register with similar functionality ? What is it called ? Where to find this information ?

Is it correct that these boards are fundamentally different in how you deal with power-settings ?

over 8 years ago

0 Amit Ashara over 8 years ago

TI__Guru**** 244450 points

Hello Ronny,

Yes, the MSP432P401R device is fundamentally different. The clocks are enabled to the peripheral block when there is an access to configure or read a register. Functional path are enabled via the enable bit in the control register. The TRM would be the right place to look for specific information on peripherals and clock management.

0 Ronny Landsverk over 8 years ago in reply to Amit Ashara

Prodigy 70 points

Hi Amit. TRM = Technical Reference Manual ?

0 Amit Ashara over 8 years ago in reply to Ronny Landsverk

TI__Guru**** 244450 points

Hello Ronny,

Yes, it is the Technical Reference Manual

www.ti.com/.../slau356h.pdf

0 Ronny Landsverk over 8 years ago in reply to Amit Ashara

Prodigy 70 points

It is not that clear to me, but I found a register SYS_PERIHALT_CTL, which is Peripheral Halt Control Register.
This register has some bits with names that are clear (HALT_DMA, HALT_ADC).
There are also HALT_eUA0/1/2/3 and HALT_eUB0/1/2/3. What are these ?
And there are HALT_T16_0/1/2/3 and HALT_T32_0. What are these ?

0 Amit Ashara over 8 years ago in reply to Ronny Landsverk

TI__Guru**** 244450 points

Hello Ronny,

This is a debug control register. This basically stalls the peripheral when the CPU is halted under debug control, as an e.g. when you are doing step debug, when the CPU is not processing any instruction, the peripheral shall not be clocked.

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MSP432P401R: Clock gating