MSP430FR2433: I/O state when LOCKLPM5 is set

Hello,

Page 318 refers to the I/O state before entry into LPM3.5 or LPM4.5.

Your understanding is not completely accurate. I/O states are locked, and register contents are lost, during the power mode transition (going into LPM4.5 in your case). Simply setting LOCKLPM5 does not clear the register contents.

Reading through your other question, for your use-case, the procedure to go into LPM4.5 and wake up from LPM4.5 is as follows:

1. Prepare I/O's for LPM4.5 by disabling all module functions (PxSEL0 and PxSEL1 = 0). Each I/O can then be set up as input, input with pullup/pulldown, or output.
2. Configure wakeup pins for wake from LPM4.5.
3. Enter LPM4.5. At this time, the I/O state (what the pin actually does) is frozen. Thus, your settings applied in #1 and #2 above are frozen at the I/O's. Once frozen, the device core is powered down, and your actual configurations of the PxDIR, PxREN, PxOUT, PxIES, and PxIE registers is lost (not readable during wakeup). However, the I/O's hold the frozen state.
4. You are now in LPM4.5.
5. Upon wakeup from an external event, the device core powers back up and the MCU goes through a reset. The I/O configuration registers go to their default values (remember, the contents were lost). However, the actual I/O states are still frozen- frozen to the settings you applied in #1 and #2 before you went to sleep.
6. You now need to re-configure the PxDIR, PxREN, PxOUT, PxIES, and PxIE registers to the correct state again (as done in #1). Once you have re-configured the I/O registers, you can then UNFREEZE the I/O's by clearing the LOCKLPM5 bit in the PMM. At this point, you are back running normally and any changes made to the I/O registers take effect immediately.

Walter

Hi Walter,

Thank you for your reply.

What mechanism is the I / O state frozen by?
There is a possibility of sleeping for a long time(2-3years) with LPM 4.5 in my application(monitoring equipment).
So during LPM4.5, I am worried whether I / O state is correctly held and remain in a state where it can wake up at any time...

Regards,
U-SK

U-SK said:

What mechanism is the I / O state frozen by?

The I/O drive logic is latched at the IO, and then it is disconnected from the I/O control registers (which are shut down) when you enter LPM4.5.

U-SK said:

There is a possibility of sleeping for a long time(2-3years) with LPM 4.5 in my application(monitoring equipment).
So during LPM4.5, I am worried whether I / O state is correctly held and remain in a state where it can wake up at any time...

I do not see any issue with specifically being able to wake up from a port interrupt after remaining in a low power mode for an extended period of time, and having the I/O ports remain latched as specified before entry into the low power mode, provided you are observing all of the other datasheet specifications (including, but not limited to things like temperature range, supply voltage range, supply voltage transients, voltages applied to I/O's, ect.).

If you have a specific concern or an issue you have seen with this, please do let us know and we can look into it.

Regards,
Walter

Hi Walter,

Thank you for your reply.

I understand.

If there are specific concerns about LPM 4.5 in the future, I will post it.

Regards,

U-SK