This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430F2013 Overflow Flag



Hi there,

 

I would like to know why the overflow flag changes when I do the next shift:

 

volatile int unsigned temp = 0x4000;

temp <<= 1;

The variable temp has 2 bytes and takes 0x8000 as its new value but I don't understand why the overflow flag (V) changes to 1.

Do you have any idea?

Thanks,

Andres Rada.

  • Hi Andres,

    were do you see this issue? Is it in the watch window?

    There was an issue with displaying variables in the watch window in earlier releases of CCS but this should be fixed in 4.1.3.

    Rgds
    aBUGSworstnightmare

  • Hi, 

    I'm working with IAR 5.10. I noticed this issue when I was watching the register SR (FLAG V). I'll try with CC4.

    Thanks for your advice,

    Andres Rada.

  • Well, the shift operation happens on assembly level. The compiler will generate an RLC or RLA instruction. The definition of both includes that an overflow occurs if the initial value is in the range of 0x40000 to 0xbfff (0x40..0xbf for 8 bit). The flag is only used for signed operations (the value overflows from 16384 to -32768). On unsigned operations, the overflow flag is simply not used by the following code.
    RLA is usually used for 8 or 16 bit shifts or the lower word of a 32 bit value, while RLC is used for the upper word of 32 bit values (or larger), as it shifts-in teh carry flag from the previous operation.

  • Hi Jens-Michael,

    Could you explain me in more detail why this SLA activate the Overflow Flag? I tried to follow the data path of this kind of instruction without any success.  

    I really appreciate your technical comments.

    Thanks,

    Andres Rada.

     

  • It's by definition. On a left shift instruction, the second most significant bit is moved into the overflow bit. Period. It's how the left shift operation is defined. If you look into the instruction description in teh MSP430 instruction set section of the users guide, you'll see a complete description of how the flags are affected by any instruction. It isn't explained, however, why this is done (even if it is obvious in most cases, like the zero flag):

    If the shift operation was meant to be performed on a value that shall be interpreted as a signed value, the following code may detect an overflow of the signed value and react, based on the overflow bit. If the value was meant to be an unsigned value, the following code just happens to ignore the existence of an overflow bit as it then isexplicitely written to not use it. Other than the carry bit, it has no effect on further operations. (and even with the carry, the compiler has the choice to either clear the bit manually, or select an operation that does not use it: RLA instead of RLC)

    For the shift operation itself, it was just 16 bits which were moved. No difference (or even knowledge) of signed or unsigned or MSB or whatever. The meaning is just an interpretation by the surrounding code, which is generated by the compiler based on teh high-level meaning of the values. The processor core itself doesn't care for the 'greater whole' of the compiler generated code.

    It's like a subtraction. If the result of a subtraction is zero, the zeroflag is set. No matter whether you care for the result being zero at all. But in case the subtraction was done with the intention of a comparison (which the cpu does not know by the instruction itself) then the zero bit is used in the following conditional jump.

    If you step through your code after the shift, you won't see any instruction dealing with the overflow bit result from this shift. It's just there in case the following code needs it, and the following code ignores it.

    And since C++ is a high-level language,there is no relevance of the existence of such things like an overflow bit at all. Across instructions, only memory contents count. What happens during a C instruction and how the compiler generates assembly code to do it, is (usually) a big black box for the C programmer. On mspgcc, there are, however, some exceptions. Liek settign the GIE bit or the LPM bits. This is why there are special compiler intrinsics exist (__BIC_SR etc.) whcih are compiled but are outside the C language scope.If these bits were in a normal function register isntead of the processor status register, there were no need for these instructions (yet it works better using the status register because of the intrrupt handling mechanisms - which is also outside the scope of the C language)

     

**Attention** This is a public forum