MSP430FR5969: Using FRAM above 0x10000 with MSPGCC 4.6.3

In case it is helpful for anyone else using Energia/MSPGCC 4.6.3 with the MSP430FR5969 we have used the following routines to copy blocks of memory to and from FRAM above 0x10000.  For some reason we have found we get errors if the watchdog timer is not disabled during the transfer.  If anyone can explain why that is it would be useful to know.

void highmem_read(uint32_t srcaddr, void *dstaddr, uint16_t len) {

disableWatchDog(); //ensure no watchdog interrupt during DMA

DMA2CTL &= ~(DMAEN | DMAIFG);
DMACTL1 = (DMACTL1 & 0xFF00) | DMA2TSEL_0;
DMA2SZ = len;

asm volatile(
"rlam.a #4, %B[srcaddr] \n\t" // Upper 16 bits need shifting
"rlam.a #4, %B[srcaddr] \n\t"// Upper 16 bits need shifting
"rlam.a #4, %B[srcaddr] \n\t"// Upper 16 bits need shifting
"rlam.a #4, %B[srcaddr] \n\t"// Upper 16 bits need shifting

"adda %B[srcaddr], %A[srcaddr] \n\t"// Combine with lower 16 bits
" \n\t"
"movx.a %A[srcaddr], &__DMA2SA \n\t"
"movx.a %[dstaddr], &__DMA2DA \n\t"
: [srcaddr] "+r" (srcaddr)
: [dstaddr] "r" (dstaddr)
: );

DMA2CTL = DMAEN | DMADT_1 | DMASRCINCR_3 | DMADSTINCR_3 | DMASBDB ;
DMACTL4 = DMARMWDIS;
DMA2CTL |= DMAREQ;
while (!(DMA2CTL & DMAIFG))
;

// Done
DMA2CTL &= ~DMAIFG;

//interrupts();
enableWatchDog();

}

void highmem_write(uint32_t dstaddr, void *srcaddr, uint16_t len) {
// Copy <len> bytes in units of 1-byte per transfer from srcaddr[] to dstaddr[]
if (!len) return;

disableWatchDog(); //ensure no watchdog interrupt during DMA

DMA2CTL &= ~(DMAEN | DMAIFG);
DMACTL1 = (DMACTL1 & 0xFF00) | DMA2TSEL_0;
DMA2SZ = len;
asm volatile(
"rlam.a #4, %B[dstaddr] \n\t" // Upper 16 bits need shifting
"rlam.a #4, %B[dstaddr] \n\t"// Upper 16 bits need shifting
"rlam.a #4, %B[dstaddr] \n\t"// Upper 16 bits need shifting
"rlam.a #4, %B[dstaddr] \n\t"// Upper 16 bits need shifting
"adda %B[dstaddr], %A[dstaddr] \n\t"// Combine with lower 16 bits
" \n\t"
"movx.a %[srcaddr], &__DMA2SA \n\t"
"movx.a %A[dstaddr], &__DMA2DA \n\t"
: [dstaddr] "+r" (dstaddr)
: [srcaddr] "r" (srcaddr)
: );
DMA2CTL = DMAEN | DMADT_1 | DMASRCINCR_3 | DMADSTINCR_3 | DMASBDB
| DMALEVEL_L;
DMA2CTL |= DMAREQ;
while (!(DMA2CTL & DMAIFG))
;
// Done
DMA2CTL &= ~DMAIFG;
enableWatchDog();
}