MSP430F5326: ADC collection result error

Part Number: MSP430F5326

    The ADC Channel 5(pin 6.5) is always connected to the GND,ADC mode is Single-channel single-conversion,Gathering many times it will occur a nonzero,the code showing as following.Please help to  confirm.
thanks

#include "msp430f5326.h"

typedef unsigned char u8;
unsigned int adsample[200];

void main(void)
{
	WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
	
	REFCTL0 &= ~REFMSTR;                      // Reset REFMSTR to hand over control to 
	// ADC12_A ref control registers
	ADC12CTL0 = ADC12ON+ADC12SHT13+ADC12SHT03+ADC12REFON+ADC12REF2_5V;
	// Turn on ADC12, Sampling time
	// On Reference Generator and set to
	// 2.5V
	ADC12CTL1 = ADC12SHP + ADC12CSTARTADD_5;    // Use sampling timer
	ADC12MCTL5 = ADC12SREF_1+ ADC12INCH_5;      // Vr+=Vref+ and Vr-=AVss
	
	for (int i=0; i<0x30; i++);                  // Delay for reference start-up
	
	ADC12CTL0 |= ADC12ENC;                     // Enable conversions
	ADC12IE = BIT5;
	P6SEL |= BIT5;                            // P6.5ADC option select
	P1DIR |= BIT1;                            // P1.0 output
	
	while (1)
	{
		ADC12CTL0 |= ADC12SC;                   // Start sampling/conversion
		
		__bis_SR_register(LPM0_bits + GIE);     // LPM0, ADC12_ISR will force exit
		__no_operation();                       // For debugger
	}
}

#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
{
	static u8 samplecount = 0;
	switch(__even_in_range(ADC12IV,34))
	{
	case  0: break;                           // Vector  0:  No interrupt
	case  2: break;                           // Vector  2:  ADC overflow
	case  4: break;                           // Vector  4:  ADC timing overflow
	case  6: break;                           // Vector  6:  ADC12IFG0
	case  8: break;                           // Vector  8:  ADC12IFG1
	case 10: break;                           // Vector 10:  ADC12IFG2
	case 12: break;                           // Vector 12:  ADC12IFG3
	case 14: break;                           // Vector 14:  ADC12IFG4
	case 16: 																	// Vector 16:  ADC12IFG5
		
		adsample[samplecount++] = ADC12MEM5;
		if(samplecount>= 160)
			samplecount = 0;
		
		if (ADC12MEM5 >= 10)                 // ADC12MEM >=10
			P1OUT |= BIT0; // Program will stop here
		else
			P1OUT &= ~BIT0;                       // P1.0 = 0
		
		__bic_SR_register_on_exit(LPM0_bits);   // Exit active CPU
		
		break;                           
	case 18: break;                           // Vector 18:  ADC12IFG6
	case 20: break;                           // Vector 20:  ADC12IFG7
	case 22: break;                           // Vector 22:  ADC12IFG8
	case 24: break;                           // Vector 24:  ADC12IFG9
	case 26: break;                           // Vector 26:  ADC12IFG10
	case 28: break;                           // Vector 28:  ADC12IFG11
	case 30: break;                           // Vector 30:  ADC12IFG12
	case 32: break;                           // Vector 32:  ADC12IFG13
	case 34: break;                           // Vector 34:  ADC12IFG14
	default: break; 
	}
}