Hello
I am working on a MSP430F5418A design and have a question regarding how the watchdog period is calculated. The reference guide indicates that the default setting configures the watchdog for a 32ms period out of reset (WDTIS =4) with SMCLK as the clock source. The bit settings for WDTIS are confusing...they assume a 32Khz clock source and have different divider values to get different periods.
I have configured my clocks to run using the DCO. The input frequency to the SMCLK is ~25Mhz. Feeding this value into the equation in the reference manual I should get a period of 781 seconds ?? This is not correct. The real period ends up being much less than a second.
How do you configure the WDTIS bits to get a period of ~20-32ms for an input clock (SMCLK) of 25Mhz?
Thanks
Rich