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Watchdog Timer period calculation for MSP430F5418A

Other Parts Discussed in Thread: MSP430F5418A

Hello

I am working on a MSP430F5418A design and have a question regarding how the watchdog period is calculated.  The reference guide indicates that the default setting configures the watchdog for a 32ms period out of reset (WDTIS =4) with SMCLK as the clock source.  The bit settings for WDTIS are confusing...they assume a 32Khz clock source and have different divider values to get different periods. 

I have configured my clocks to run using the DCO.  The input frequency to the SMCLK is ~25Mhz.  Feeding this value into the equation in the reference manual I should get a period of 781 seconds ??  This is not correct.  The real period ends up being much less than a second.

How do you configure the WDTIS bits to get a period of ~20-32ms for an input clock (SMCLK)  of 25Mhz?

 

Thanks

Rich

  • Hi Rich,

    Yes, it's a bit confusing.  But the result of the formula is Hz. 

    So if you use WDTIS = 4 with a 25MHz clock source, your watchdog interval yields 781Hz, which is a 1/781 = 1.28 millisecond period.

    Seems like WDTIS = 3 (for /512K) works for you.  25MHz/512K = 48Hz or 21ms.

    Jeff

  • The WDT is actually not a "timer". It counts pulses, when the count reaches certain full count number, it generates a reset or an interrupt.

    So-called WDTSSEL (2 bits) select one of four alternative sources of pulses (SMCLK, ACLK, VLOCLK, or X_CLK).

    So-called WDTIS (3 bits) select one of eight full count numbers (2147483648, 134217728, 8388608, 524288, 32768, 8192, 512, or 64).

    In your case, the default ~25MHz clock with full count number 32768, should take 32768 / 25MHz = 1310.72usec (i.e., ~1.3msec).

    If you set WDTIS to 3 instead of 4, it should take 524288 / 25MHz = 20971.52usec (i.e., ~21msec).

     

  • Thanks Jeff

    That did the trick!

     

    Rich

  • Thanks old_cow_yellow

    That worked!

     

    Rich

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