Hi,
I've got a problem with SPI communication: the first transmitted byte measured using oscilloscope is wrong: I read with the oscilloscope 0x104 (0b100000100) (9 clock cycles!!!) not 0x04(0b00000100) (8 clocks)
Here's the main():
WDTCTL = WDTPW | WDTCNTCL; // watchdog is on
P1REN = 0x1B; // Terminate unavailable Port1 pins (P1.0/1/3/4) properly, Config as Input with pull-down enabled
BCSCTL3 |= LFXT1S_2; // Select VLO as low freq clock
BCSCTL2 |= DIVS_1; // SMCLK = 0.5 MCLK 0 WD reset each 64 ms
P1OUT |= BIT2;
P1DIR |= BIT2 | BIT5 | BIT6 | BIT7; // setup port 1 outputs
USICTL0 |= USIPE7 | USIPE6 | USIPE5 | USIMST | USIOE; // Port, SPI master
USICTL1 |= USICKPH; // set the phase
USICKCTL = USIDIV_1 | USISSEL_2; // SPI clk = /2 SMCLK, low clock polarity
USICTL0 &= ~(USISWRST); // USI released for operation
/* USISRL = 0x04; // data register address
USICNT = 8; // re-load counter
__delay_cycles(40); // Add time between transmissions to make sure slave can process information
*/
P1OUT &= ~BIT2; // CS DAC
__delay_cycles(4);
USISRL = 0x04; // data register address
USICNT = 8; // re-load counter
__delay_cycles(40); // Add time between transmissions to make sure slave can process information
USISRL = 0xA0; // data
USICNT = 8; // re-load counter
__delay_cycles(40); // Add time between transmissions to make sure slave can process information
USISRL = 0x0; // data
USICNT = 8; // re-load counter
__delay_cycles(40); // Add time between transmissions to make sure slave can process information
P1OUT |= BIT2; // CS DAC
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/interrupt
When I add a dummy write (commented out section of code) while Chip Select line is inactive the communication works fine. Any ideas why MSP adds one clock at the begining?
