Other Parts Discussed in Thread: ENERGYTRACE, MSP-FET, , MSP430G2955
Hopefully someone can give me some insight into what I may be doing wrong.
Testing only the microcontroller in active mode running with the internal VLO with a div/8 clock reported higher than expected current consumption. The measured current was calculated by measuring the voltage drop across a 12k resistor.
The current consumption was expected to be in the order of 10uA however the measured current is always in the order of 40uA.
The circuit is constructed using a benchtop power supply a 12kOhm resistor and the MSP430 in active mode. Current is measured by measuring the voltage drop across the resistor and calculating the current. I=(Vs – Vuc)/R.
Checking the internal startup of all the uC registers highlights that the internal uC modules start up in either a hold, reset or off state. Eg low power consumption state. Port bits were placed in the output direction with resistor enable turned off as per the recommendation. The SVS is in the off state and the comparator is turned off.
The PCB has been ruled out as the source of error as the same code was tested on two different boards and the another the MSP-TS430PM64 programming board. It should be noted that J6 and J7 are not jumpered on the programming board.
Unused pins are connected as per the unused pin section in the data sheet. The 32KHz crystal has also been removed to ensure this is not a crystal related problem.
Here is the unused pin connection list.
|
Pin name |
Pin location |
Setting |
|
Vref+ |
|
Open |
|
Veref+ |
10 |
GND |
|
Vref-/Veref- |
11 |
GND |
|
Xin |
8 |
Vcc |
|
Xout |
|
Open |
|
XT2in |
53 |
Gnd |
|
XT2Out |
|
Open |
|
Px0 to Px.7 |
|
Outputs driven high also tried low |
|
nRST/NMI |
47kOhm with10nF pulldown |
|
|
Test |
|
Open |
|
TDO |
|
Open |
|
TDI |
|
Open |
|
TMS |
|
Open |
|
TCK |
|
Open |
Here is the test code.
#include <msp430.h> #define WDTSOURCE 0x04 // tACLK * 2^15 = 1 s @ 32768 Hz int main(void) { __disable_interrupt(); WDTCTL = WDTPW | WDTHOLD | WDTCNTCL | WDTSOURCE; IE1 = 0; BCSCTL1 = 0xb0; // XT2 off, LFXT1 low freq, ACLK/8, RSELx=0 BCSCTL2 = 0xfe; // LFXT1CLK for MCLK and SMCLK, MCLK/8, SMCLK LFXT1CLK, SMCLK/8 BCSCTL3 = 0xe4; //********** test VLOCLK instead of 32K LFXT1 Hardware_CLOCK_CONFIG; DCOCTL = 0x00; // DCOx=0, MODx=0 __bis_SR_register(SCG0 | SCG1); // DCO and SMCLK off /* P1SEL = 0; P1DIR = 0; P1OUT = 0; P1REN = 0xff; P1IFG = 0; P2SEL = 0; P2DIR = 0; P2OUT = 0; P2REN = 0xff; P2IFG = 0; P3SEL = 0; P3DIR = 0; P3OUT = 0; P3REN = 0xff; P4SEL = 0; P4DIR = 0; P4OUT = 0; P4REN = 0xff; P5SEL = 0; P5DIR = 0; P5OUT = 0; P5REN = 0xff; P6SEL = 0; P6DIR = 0; P6OUT = 0; P6REN = 0xff; */ P1SEL = 0; P1DIR = 0xff; P1OUT = 0xff; P1REN = 0; P1IFG = 0; P2SEL = 0; P2DIR = 0xff; P2OUT = 0xff; P2REN = 0; P2IFG = 0; P3SEL = 0; P3DIR = 0xff; P3OUT = 0xff; P3REN = 0; P4SEL = 0; P4DIR = 0xff; P4OUT = 0xff; P4REN = 0; P5SEL = 0; P5DIR = 0xff; P5OUT = 0xff; P5REN = 0; P6SEL = 0; P6DIR = 0xff; P6OUT = 0xff; P6REN = 0; /* ADC12CTL0 = 0; ADC12CTL1 = 0; TACTL = 0; TBCTL = 0; UCA0CTL1 = 0x01; // hold in reset UCA1CTL1 = 0x01; SVSCTL = 0; */ P5SEL &= ~0x01; P5DIR |= 0x01; for (;;) { // P5OUT ^= 0x01; } return 0; }
