CC430F5137: the power consumption during LPM3 sleep period is high

Hello Derong,

It looks like the third and fourth screenshots are identical to the first two. For those screenshots, the operation seems normal: sleep, wake-up, go back to sleep. For the last screenshot, I can see where the device seems to be coming out of LPM3 mode, but I'm not sure why it's behaving like this. It doesn't seem to fully wake up like the first and third screenshots.

In the last screenshot, when the current goes to 1mA, is this the device supposed to wake up completely? What's the bottom scale in units of time? uS? I suspect that this issue is caused by an errata (which seem to be many unfortunately). I would recommend starting with one of our LPM3 code examples for the CC430F5137, implementing the errata workarounds, and measuring the current. Then, start adding your code piece by piece to see what's causing this strange start-up behavior.

cc430x513x_LPM3_1.c

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//******************************************************************************
//   CC430x513x Demo - Enters LPM3 (ACLK = LFXT1)
//
//   Description: Configure ACLK = LFXT1 and enters LPM3. Measure current.
//   Note: SVS(H,L) & SVM(H,L) are disabled
//   ACLK = LFXT1 = 32kHz, MCLK = SMCLK = default DCO
//
//                 CC430x513x
//             -----------------
//        /|\ |              XIN|-
//         |  |                 | 32kHz
//         ---|RST          XOUT|-
//            |                 |
//
//   M. Morales
//   Texas Instruments Inc.
//   April 2009
//   Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************

#include <msp430.h>

int main(void)
{  
  WDTCTL = WDTPW+WDTHOLD;                   // Stop WDT

  P5SEL |= BIT0 + BIT1;                     // Select XT1
  UCSCTL6 |= XCAP_3;                        // Internal load cap

  // Loop until XT1,XT2 & DCO stabilizes
  do
  {
    UCSCTL7 &= ~(XT1LFOFFG + DCOFFG);
                                            // Clear LFXT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

  UCSCTL6 &= ~(XT1DRIVE_3);                 // Xtal is now stable, reduce drive
                                            // strength

  P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; P5OUT = 0x00;
  P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; P5DIR = 0x03;
  
  PJOUT = 0x00;
  PJDIR = 0xFF;

  // Turn off SVSH, SVSM
  PMMCTL0_H = 0xA5;
  SVSMHCTL = 0; 
  SVSMLCTL = 0; 
  PMMCTL0_H = 0x00; 

  __bis_SR_register(LPM3_bits);             // Enter LPM3
  __no_operation();                         // For debugger
}

Regards,

James

MSP Customer Applications

Sorry I uploaded the wrong image file. The correct should look like this:

In the last screenshot, the device should wake up for 1ms and then back to sleep.

The Errata issued in May 2018 mentioned some bugs in CC430F5137 can corrupt the PC/SR register. I have contacted with IAR for adding a flag in the compiler option. They should tell me if adding the flag can resolve the problem.

I am also testing my software with  what the errata suggested in the workaround:

1. adding the flag 

2. setting MCLK divide by 2

3. use XT2 as the SMCLK oscillator source

I found the 1mA problem occurred 5 times in the 17-hour test record but the 1mA did not last as long as in the old test record.

This weekend I will test the code with adding "Turn off SVSH, SVSM before entering LPM3" as suggested in your comment and post the test result next Monday.

Thanks,

Derong Yuan

Seabreeze International Corporation

2018-7-13

Sorry my laptop got a power reset this weekend so I will run the test again.

I tested what listed in the workaround for PMM12 and found if use XT2 as the SMCLK oscillator source instead of the DCO CC430F5137 will consume much more power. So I have no choice but to try enable SMCLKREQEN in register UCSCTL8 and run the test again.

this is the setting for all clock control registers:
//------------------------------------------------------------------------------
/* MCU clock system (UCS) initialization
* - Start the 32768Hz crystal oscillator XT1
* - Configure the FLL to generate 8MHz clock using XT as reference
* - MCLK = SMCLK = 244 * fXT1 = 7.995392MHz from DCO/2.
*/
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.

UCSCTL6 = XT2OFF & msk_1 | //XT2 is off
XT1OFF & msk_1; // XT1 is Off

__bis_SR_register(SCG0); // disable FLL pulling of DCO
UCSCTL0 = 0x0000; // set DCO to lowest tap
// FLL loop divide-by-2, Fsys/Fxt1 ratio = 243+1 = 244
UCSCTL2 = FLLD__2 | 243;
UCSCTL1 = DCORSEL_5; // good for 10..20MHz, we run Fdco = 16MHz and divide
// by 2 to make sure that clock duty cycle = 50% since
// we run at the 8MHz max limit for PMMCOREV = 0.
__bic_SR_register(SCG0); // re-enable FLL control
// maximum FLL settling delay = 1024 * f_MCLK / f_FLLREF
__delay_cycles(250000lu);

bTimeout = 100; // try max 100ms
// wait for ALL oscillator fault flags to become clear
while (SFRIFG1 & OFIFG)
{
__delay_cycles (8000lu); // delay ~1ms
// clear individual flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // clear sum flag
if (--bTimeout == 0)
{
//something wrong
SOFTWARE_BOR_REBOOT
}
}

//set SMCLKREQEN bit 1 in UCSCTL8 register: SMCLK conditinal requests are enabled
UCSCTL8 |=SMCLKREQEN;

//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default)
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

This is my test result for PMM12
1. use DCO as the SMCLK oscillator source

2.use XT2 as the SMCLK oscillator source instead of the DCO

3. use DCO as the SMCLK oscillator source but set SMCLKREQEN bit 1 in UCSCTL8 register: SMCLK conditinal requests are enabled

I have another question on your suggestion to add the codes to turn off SVSH and SVSM but I do not know if the codes should be added in the init process of the software which will be executed only once or just before the LPM3 instruction as shown below which will be executed in the BIG loop.
//=====================================================
// MAIN LOOP
//=====================================================
while (1)
{
CLRWDT_16s

//make VLO (10khz) as ACLK's clock source
UCSCTL4 = SELA__VLOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

..........

// Turn off SVSH, SVSM
PMMCTL0_H = 0xA5;
SVSMHCTL = 0;
SVSMLCTL = 0;
PMMCTL0_H = 0x00;

//set MCLK divide by 2
UCSCTL5 = (UCSCTL5 & 0xFFF0) | DIVM__2;
__bis_SR_register(LPM3_bits + GIE); //enter LPM3 and re-enable interrupts


// CPU SLEEPS HERE!
__delay_cycles (800ul); //waiting
//set MCLK divide by 1 
UCSCTL5 = UCSCTL5 & 0xFFF0;


SFRIE1 &= ~WDTIE; // disable WDT interrupt
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default)
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

//==========================================
// Handle pending wake-up flags
//==========================================
CLRWDT_16s

Derong Yuan

Seabreeze International Corporation

2018-7-16

Sorry my laptop got a power reset in the weekend so I will run the test again.

But I have a question here on the workaround of the PMM12: how much current will be added If the SMCLK use XT2 as the oscillator source instead of the DCO ? In my current software I turned off both XT1 and XT2 in UCSCTL6.

Below shows the XT2 is turned on:

//------------------------------------------------------------------------------
/* MCU clock system (UCS) initialization
* - Start the 32768Hz crystal oscillator XT1
* - Configure the FLL to generate 8MHz clock using XT as reference
* - MCLK = SMCLK = 244 * fXT1 = 7.995392MHz from DCO/2.
*/
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
//UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.
UCSCTL4 = SELA_2+SELS_5+SELM_3; //ACLK = REFO, MCLK=DCOCLK. SMCLK=XT2


UCSCTL6 = XT2OFF & msk_0 | //XT2 is on 
XT1OFF & msk_1; // XT1 is Off 

__bis_SR_register(SCG0); // disable FLL pulling of DCO
UCSCTL0 = 0x0000; // set DCO to lowest tap
// FLL loop divide-by-2, Fsys/Fxt1 ratio = 243+1 = 244
UCSCTL2 = FLLD__2 | 243; 
UCSCTL1 = DCORSEL_5; // good for 10..20MHz, we run Fdco = 16MHz and divide
// by 2 to make sure that clock duty cycle = 50% since
// we run at the 8MHz max limit for PMMCOREV = 0.
__bic_SR_register(SCG0); // re-enable FLL control
// maximum FLL settling delay = 1024 * f_MCLK / f_FLLREF
__delay_cycles(250000lu); 

bTimeout = 100; // try max 100ms
// wait for ALL oscillator fault flags to become clear
while (SFRIFG1 & OFIFG) 
{
__delay_cycles (8000lu); // delay ~1ms
// clear individual flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); 
SFRIFG1 &= ~OFIFG; // clear sum flag
if (--bTimeout == 0)
{
//something wrong
SOFTWARE_BOR_REBOOT 
} 
}
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default) 
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

Another question is the turning off both SVSH and SCSM instructions be executed once  in the hardware init or once-per-looping before the LPM3 instruction in the MAIN LOOP as shown below?

//=====================================================
// MAIN LOOP
//=====================================================

while(1)

{

CLRWDT_16s

//make VLO (10khz) as ACLK's clock source
UCSCTL4 = SELA__VLOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

..........

WDTCTL =WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL_2+WDTIS1; //1/16s
SFRIE1 |= WDTIE; // Enable WDT interrupt 

// Turn off SVSH, SVSM
PMMCTL0_H = 0xA5;
SVSMHCTL = 0;
SVSMLCTL = 0;
PMMCTL0_H = 0x00;

//set MCLK divide by 2
UCSCTL5 = (UCSCTL5 & 0xFFF0) | DIVM__2;
__bis_SR_register(LPM3_bits + GIE); //enter LPM3 and re-enable interrupts


// CPU SLEEPS HERE!
__delay_cycles (800ul); //waiting
//set MCLK divide by 32
UCSCTL5 = UCSCTL5 & 0xFFF0;


SFRIE1 &= ~WDTIE; // disable WDT interrupt
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default)
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;
//delay_cycles(x) is stopping in the code and waiting for x MCLK cycles

//==========================================
// Handle pending wake-up flags
//==========================================
CLRWDT_16s

.........

}

Thanks,

Derong Yuan