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MSP432P401R: I2C spec testing

Janet Shen
Expert 7795 points

Part Number: MSP432P401R

Dear Champs,

Our customer test MSP432P FS mode I2C but met some problem. I tried to test our I2C module and met the similar problem.

  • Used two MSP-EXP432P401R boards
  • Test code: msp432p401x_euscib0_i2c_10 as master and msp432p401x_euscib0_i2c_11 as slave
  • Modify system clock (__SYSTEM_CLOCK) as 12MHz
  • Rs: 1)4.7K, 2)10K, 3)2K

But set SCL as 400KHz and then measured it, we got below result:

Rs SCL result
4.7K 365KHz
10K 376K
2K 395KHz

And I also studied I2C bus spec from datasheet, we do not provide value of tHIGH, tLOW, tF, tR. 

When I look at the code, the SCL clock source is SMCLK from DCO.

Does DCO accuracy result it SCL offset? Or Cp? Or Rs? 

Although we use logic analyzer, we could identify all I2C packet. But customer care about I2C physical parameter. 

Do you have any suggestion for this?

Please feel free to let me know if you have any comment.

Thanks a lot.

  • 0
    TI__Guru 55136 points

    Janet,

       Can you also confirm the DCO by outputing MCLK?

        P4->DIR |= BIT2 | BIT3;
    P4->SEL0 |= BIT2 | BIT3;                // Output ACLK & MCLK
    P4->SEL1 &= ~(BIT2 | BIT3);

    CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access
    CS->CTL0 = 0;                           // Reset tuning parameters
    CS->CTL0 = CS_CTL0_DCORSEL_3;           // Set DCO to 12MHz (nominal, center of 8-16MHz range)
    // Select ACLK = REFO, SMCLK = MCLK = DCO
    CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;
    CS->KEY = 0;                            // Lock CS module from unintended accesses

    The DCO will directly impact SCL.  However, it is not clear how the load (pullup resistor or capacitance) would impact the DCO.  Perhaps another test is to use the HFXT on the launchpad in place of the DCO.  Can you also confirm the duty cycle of the DCO and SCL?

    Regards,

    Chris

  • 0 in reply to Chris Sterzik
    TI__Expert 7795 points
    Dear Chris,

    Yes, I have used above code (from msp432p401x_cs_01) add to output MCLK, the result during 12.01~12.07MHz. (Have modified system clock (__SYSTEM_CLOCK) as 12MHz on system_msp432p401r.c). How do I increase the frequency accuracy to let SCL as 400KHz?

    If you have any suggestion, please feel free to let me know.
    Thanks a lot.
  • 0 in reply to Janet Shen
    TI__Expert 7795 points
    Dear Chris,

    I also changed clock source to HFXT (copied the clock setting from msp432p401x_cs_09) on msp432p401x_euscib0_i2c_10 to test I2C master .
    But it still met the same result.

    And the duty cycle of the DCO and SCL is 49%~51% no matter on DCO or HFXT.

    Do you have any idea or suggestion for this issue?
    Please feel free to let me know if any comment.
    Thanks a lot.
  • 0 in reply to Janet Shen
    TI__Guru 55136 points
    Janet,
    I am seeing what appears to be an overhead or synchronization issue between the SMCLK and the I2C bit clock. It looks like about 3 cycles. I have not tested with different pull-up values, but with a 10K pullup I am seeing the following relationships:

    /* Desired (SMCLK/BRW) Actual ?BRW (logic analyzer SMCLK transitions)
    * 12M/32 -> 375Khz 342Khz 35 (70)
    * 12M/30 -> 400Khz 361Khz 33 (66)
    * 12M/27 -> 444Khz 400Khz 30 (60)
    */

    I am going to close this thread and continue the investigation internally.

    Regards,
    Chris
  • 0 in reply to Chris Sterzik
    TI__Expert 7795 points
    Dear all,

    Closed this issue at this moment. And will update later.
    Thanks for all help.

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