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MSP430G2553: Timer A1 & CCR2 as PWM controller - malfunctioning under heavy CPU load

Keir Stitt36
Prodigy 30 points

Part Number: MSP430G2553

Hello,

I am using the above MSP430G2553 microcontroller and need to generate a PWM signal which I am doing with Timer A1 and its CCR2.

I have set the clock source as SMCLK and operating mode as OUTMOD_7 (Reset/SET). TA1CCR0 is handset in code to 0x00FF in order to set the PWM Period. TA1CCR2 is set in software to set the duty cycle.

Even when I set TA1CCR2 to always be equal to a constant and don't touch it anywhere else in code, my output signal is asserting itself to high for random periods of time.

I have ensured that the micro controller never enters into sleep mode. The problem seems to go away when I turn off GIE, so I suspect that I might have a stack overflow problem in my code, but even if I have then this should never happen. I have a break point at boot and the microcontroller is never resetting.

I have read the device Errata and there's a few comments about erroneous interrupts etc on Timer A. But nothing in the datasheet, manual or errata to suggest that this should be happening.

Have I missed something? Is there something that could be perhaps causing this that I've missed?

Regards, Keir

  • 0
    Guru 325440 points
    Are any of the timer's register modified elsewhere in the code (especially in an interrupt handler)?
  • 0 in reply to Clemens Ladisch
    TI__Guru 56685 points
    Hello Keir,

    One issue I can see here is if you have either numerous interrupts from different sources, or long interrupts, you could be starving the Timer interrupts thus causing a delay in their servicing and thus a glitch or blip in you PWM.

    For example, it could be an issue with interrupt priority where a frequent higher priority interrupt source or sources are constantly or very rapidly being set. thus the timer interrupt doesn't get serviced in time to make sure the PWM is not affected. Alternatively, you could have long ISR (regardless of priority) in which you are still in the ISR routine of another interrupt when the Timer interrupt comes in. Thus the Timer interrupt cannot be serviced for another ISR is till running.

    I would suggest doing most of your operations that are in ISRs in you main code loop. to do this, just make flags that your ISRs set/clear that you check in your main loop to perform actions. That way you limit the time in which you are servicing other ISRs sot he Timer ISR can be serviced.
  • 0 in reply to Jace H
    Guru 325440 points

    you could be starving the Timer interrupts

    Generating PWM with OUTMOD_7 does not require interrupts.

    The only way to affect the output is by messing around with the hardware (clock or timer).

  • 0 in reply to Jace H
    Prodigy 30 points

    Thanks Jace H,

    Unfortunately I have a UART interface that is extremely busy, and its ISR fires often as a result. Although according to the datasheet both timer modules have a higher Interrupt priority than UART or the ADC that i am also using.

    Although I'm still confused as surely being a hardware module for which I am not concerned with its own interrupts, TimerA and its CCP module should be able to continue to produce a PWM waveform regardless of the state of the rest of the microcontroller except for power and clock.

    Does the CCP module depend on the interrupt state, even when its own interrupt enable is switch off?

    In an ideal world I would have chosen a microcontroller with a DMA controller so that I wouldn't have to worry about all the UART interrupts. But as they are only transferring data from memory these ISR's are very quick to execute, just extremely frequent.

    Regards, Keir

  • 0 in reply to Clemens Ladisch
    Prodigy 30 points
    No, I've searched everywhere for the timers registers. They are only referenced in the initialisation routine and a single PWM update routine, and as mentioned in the original post, if i comment out the line in the update routine that writes to TACCR2 then the problem remains.

    Of course the Timer is using the SMCLK which could potentially be switched off in some power modes, but again I've ensured that it never enters into a low power mode.

    The update routine is in the main loop and not on an interrupt - although it is triggered by a state machine which is updated from the ADC interrupt.
  • 0 in reply to Keir Stitt36
    Guru 325440 points
    When you output SMCLK to P1.4, does it look OK?
  • 0 in reply to Clemens Ladisch
    TI__Guru 56685 points
    Although true the timer will output the correct pulse width with no intervention, if you want to change that pulse width from cycle to cycle with no or imperceptible "glitches" in the signal, then you want to change the CCR value within the TIMER ISR after a full cycle has past. this is especially important in say creating a PWM DAC for Sound output. (Please see www.ti.com/.../TIDM-VOICEBANDAUDIO ) The linked project is the main reason why I mention this possibility as I had a similar issue when first creating that project.
  • 0 in reply to Jace H
    TI__Guru 56685 points
    Keith,

    Without seeing the exact waveform and timer settings, I can't be sure what the issue is. That being said, another avenue to look at is to see if you can increase your MCLK frequency so the device uses less time to process ISRs and get through your main loop.

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