MSP430F5529: Chip Lockup when configuring XT2, DCO and XT1

Hi, 

We have  an MSP430 based product that is experiencing some random lockup issues.   When the chip locks up the MSP-FET debugger is unable to communicate, and we get a 

MSP430: Trouble Halting Target CPU: Internal error

message.  

The device has a 32768 Crystal on XT1 and a 24Mhz Crystal on XT2.   During LPM we disable the XT2.   The processor runs off of the DCO and the peripherals are running off of the XT2 when we are awake.

The issue comes about when the device is asynchronously awakened,  and we enter the lockup state at varying rates depending on the particular board we test.   In the worst case we will lock up 1/3 times in the best case it will go hundreds of times without a  lockup. 

We have been able to track the issue down to the following routine, that runs when we come out of low power mode (LPM3).

Any thoughts ? 

/*  

 * ======== Init_Clock ========

 */

VOID Init_Clock (VOID)

{

// DISABLE interrupts until clock is reconfigured

int key = Hwi_disable();

// Turn on a debug LED for tracking the lockup issue

LED_ERROR_ON;



//  Configure the Crystal selection port

P5SEL |= BIT2+BIT3+BIT4+BIT5;                   // Port select XT2 and XT1



// Enable the FLL

__bis_SR_register(SCG0);



// Set the FLL Initial parameters to Values from after the FLL settled at boot up. 

  UCSCTL0 = FLLSaveCtl0; // Get Clock Going at initial rate

  UCSCTL1 = FLLSaveCtl1;

 

  UCSCTL6 &= ~(XT1OFF+XT2OFF);      // Enable Both Crystals



// Initializes the clocks.  Starts the DCO at USB_MCLK_FREQ (the CPU freq set with the Desc 

// Tool), using the REFO as the FLL reference.  Configures the high-freq crystal, but 

// doesn't start it yet.  Takes some special actions for F563x/663x.  

//

// Assumptions are that there is an external 24MHz and 32.768KHz oscillators. The internal 32.768Khz

// This code sets up MCLK = 24MHz, SMCLK = 1MHz and ACLK = 32.768KHz.  

  // Loop until XT1,XT2 & DCO stabilizes

  do

  {

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                      // Clear fault flags

  }while ((SFRIFG1&OFIFG) || (UCSCTL7 & (XT2OFFG + XT1LFOFFG + DCOFFG)) );                   // Test oscillator fault flag







  UCSCTL6 &= ~(XT1DRIVE0+XT1DRIVE1);                    // Decrease XT1 Drive according to

  // expected frequency



  UCSCTL4 = SELS_5 + SELM_3 + SELA_0;      // SMCLK=XT2 MCLK=DCO, ACLK = XT1



  // Disable LED for Diag purposes

  LED_ERROR_OFF;



  // Restore hardware interrupts if necessary

  Hwi_restore(key);

}