Part Number: MSP430FR2433
Champs,
I am asking this for our customers.
They are suffering the errata ESCI47
P8 of
http://www.ti.com/lit/er/slaz664l/slaz664l.pdf
because they have to set SPI clock pin pulled-up by default for the host to boot up on their board, which meets the conditions of ESCI47 in this case.
MSP430FR2433IRGE acts as SPI slave with UCCKPH=1, UCCKPL=0, and they have to use this setting because of host SPI limitation.
Now, they want to implement a workaround based on the errata, and it seems only the second way can be used because there is not interrupt between FR2433 and the host.
The idea is:
After FR2433 boots-up, they will use the host to reset FR2433 again with SPI clock pulled-low before, during and after MSP430 is resetting.
The timing diagram is as follows:
Would you please help confirm if this can be used as a workaround to resolve this USCI47 erratum or if there is any other concern?
Wayne Huang
