CCS/MSP430F5529: error #10234-D: unresolved symbols remain

/*
* LORA.c
*
*/
#include "LORA.h"
#define LoRa_Frequency 868000000
#define LoRa_PA_Boost_Pin 1
#define LoRa_Output_RFO_Pin 0
/*Global Variables*/
volatile uint8_t implicit_header_mode=0;
volatile uint8_t modem=0;
volatile uint8_t node_address=0;
volatile uint8_t bandwidth = BW_125;
volatile uint8_t RSSI=0;
volatile uint8_t requestAck=0;
volatile uint8_t destination=0;
volatile uint8_t packetNumber=0;
volatile uint8_t payloadlength=0;
struct pack packet_sent;
/*
* Initialize SPI USCI and Reset pin of LORA
* UCA0
* P2.0 - NSS
* P3.4 � UCA0SOMI
* P3.3 � UCA0SIMO
* P2.7 � UCA0CLK
* P1.5 - RESET
* */
void SPI_Initialize(){
 /*Make Pin 1.5 Output*/
 P1OUT |= BIT5;
 P1DIR |= BIT5;
 /*Make Pin 2.0 Output For NSS*/
 P2OUT |= BIT0;
 P2DIR |= BIT0;
 P3SEL |= BIT3+BIT4; // P3.3,4 option select
 P2SEL |= BIT7;
 UCA0CTL1 = UCSWRST;
 UCA0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC; // 3-pin, 8-bit SPI master
 UCA0CTL1 |= UCSSEL_2; // SMCLK
 UCA0BR0 |= 0x02; // /2
 UCA0BR1 = 0; //
 UCA0MCTL = 0; // No modulation
 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
/*
* Milisecond Delay using intrinsic delay function
* For 8MHz Clock speed
* */
void DELAY_Ms(uint16_t ms){
 while(ms>0){
 __delay_cycles(4000);
 ms--;
 }
}

/*
* Second Delay using intrinsic delay function
* For 8MHz Clock speed
* */
void DELAY_Sec(uint8_t sec){
 while(sec>0){
 DELAY_Ms(1000);
 sec--;
 }
}
/*
* Function to Send Byte Data to Slave over SPI
* */
void SPI_Send_Byte(uint8_t Data){
 while (!(UCA0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
 UCA0TXBUF = Data; // Send 0xAA over SPI to Slave
 while (!(UCA0IFG & UCTXIFG));
 //DELAY_Ms(1);
}
/*
* Function to Receive Byte Data from Slave over SPI
* */
uint8_t SPI_Receive_Byte(){
 while (!(UCA0IFG & UCRXIFG)); // USCI_A0 RX Received?
 uint8_t data=0;
 data = UCA0RXBUF; // Store received data
 return data;
}
/*
* LoRa Module Initialization Function
* */
void LORA_Init(){
 SPI_Initialize();
 /*Set NSS High*/
 P2OUT |= BIT0; // NSS High
 /*Cycle Reset of LoRa module*/
 P1OUT &= (~BIT5); // RESET low
 DELAY_Ms(10);
 P1OUT |= BIT5; // RESET High
 DELAY_Ms(10);
 /*Get LoRa Module Version*/
 uint8_t module_version=0;
 module_version = LORA_Read_Register(RegVersion);

 /*Check if version is valid*/
 if (module_version != 0x12)
 while(1);
 /*Calibrate Rx Chain*/
 LORA_Rx_Chain_Cal();
 /*Set Max Current to 100mA*/
 LORA_Set_Max_Current(0x1B);
 /*Put Module in LoRa Mode*/
 LORA_Set_Lora_Mode();
 /*Set CRC On*/
 LORA_Set_CRC(1);
 /*Set Default sync word for non LoRaWAN*/
 LORA_Set_Sync_Word(0x12);
}
/*
* Read the value of a specific register from
* LoRa Module
* */
uint8_t LORA_Read_Register(uint8_t reg){
 /*Translate Address*/
 uint8_t addr=reg & 0x7f;
 /*Set NSS Low*/
 P2OUT &= (~BIT0);
 SPI_Send_Byte(addr);
 SPI_Send_Byte(0x00);
 uint8_t value;
 value = SPI_Receive_Byte();
 /*Set NSS High*/
 P2OUT |= (BIT0);
 return value;
}
/*
* Write to the value of a specific register from
* LoRa Module
* */
void LORA_Write_Register(uint8_t reg, uint8_t value){
 /*Translate Address*/
 uint8_t addr=reg | 0x80;
 /*Set NSS Low*/
 P2OUT &= (~BIT0);
 SPI_Send_Byte(addr);
 SPI_Send_Byte(value);
 /*Set NSS High*/
 P2OUT |= (BIT0);
}

/*
* Set frequency of the LoRa Module
* */
void LORA_Set_Frequency(uint32_t frequency){
 uint8_t state;
 /*Save the current state*/
 state=LORA_Read_Register(RegOpMode);
 /*Check if modem is in LoRa Mode*/
 if(modem == LORA)
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 else
 LORA_Write_Register(RegOpMode, ModeFskStandby);
 uint32_t f,f1;
 f = ((frequency >> 16) & 0x0FF); // frequency channel MSB
 LORA_Write_Register(RegFrfMsb, f);
 f = ((frequency >> 8) & 0x0FF); // frequency channel MIB
 LORA_Write_Register(RegFrfMid, f);
 f = (frequency & 0xFF); // frequency channel LSB
 LORA_Write_Register(RegFrfLsb, f);
 DELAY_Ms(100);
 /*verify*/
 f=LORA_Read_Register(RegFrfMsb);
 /*save MSB in f1*/
 f1=(f<<8) & 0xFFFFFF;
 /*retrieve mid bit*/
 f=LORA_Read_Register(RegFrfMid);
 /*save mid byte in f1 */
 f1= (f1<<8) + ((f<<8) & 0xffffff);
 /*retrieve lsb*/
 f=LORA_Read_Register(RegFrfLsb);
 /*save lsb in f1*/
 f1= (f1) + (f & 0xffffff);
 /*Loop here is frequencies dont match*/
 while(f1!=frequency);
 /*restore state*/
 LORA_Write_Register(RegOpMode,state);
 DELAY_Ms(100);
}
/*
* Set Output power of the LoRa Module
* */
void LORA_Set_Power(int8_t dbm,uint8_t OP){
 int8_t power;
 power = dbm;
 if (LoRa_Output_RFO_Pin == OP) {
 // RFO
 if (power < 0) {
 power = 0;
 } else if (power > 14) {
 power = 14;
 }
 LORA_Write_Register(RegPaConfig, 0x70 | power);
 } else {
 // PA BOOST
 if (power < 2) {
 power = 2;
 } else if (power > 17) {
 power = 17;
 }
 LORA_Write_Register(RegPaConfig, LoRa_PA_Boost | (power - 2));
 }
}
/*Set dBm only*/
void LORA_Set_Power_Db(int8_t dbm){
 uint8_t state,value;
 state=LORA_Read_Register(RegOpMode);
 LORA_Set_Lora_Mode();
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 uint8_t pmax=15;
 value = dbm-pmax + 15;
 value = value | 0b10000000;
 LORA_Write_Register(RegPaConfig, value);
 DELAY_Ms(10);
 while(value!=LORA_Read_Register(RegPaConfig));
 LORA_Write_Register(RegOpMode, state);
 DELAY_Ms(100);
}
/*
* Set Spreading Factor of the LoRa Module
* */
void LORA_Set_Spreading_Factor(uint8_t spFactor){
 int8_t config,config1;
 uint8_t state;
 state=LORA_Read_Register(RegOpMode);
 LORA_Set_Lora_Mode();
 LORA_Write_Register(RegOpMode, ModeLoraStandby);

 config=LORA_Read_Register(RegModemCfg2);
 switch(spFactor)
 {
 case SF_6: config = config & 0b01101111; // clears bits 7 & 4 from REG_MODEM_CONFIG2
 config = config | 0b01100000; // sets bits 6 & 5 from REG_MODEM_CONFIG2
 LORA_Implicit_Header(); // Mandatory headerOFF with SF = 6
 break;
 case SF_7: config = config & 0b01111111; // clears bits 7 from REG_MODEM_CONFIG2
 config = config | 0b01110000; // sets bits 6, 5 & 4
 break;
 case SF_8: config = config & 0b10001111; // clears bits 6, 5 & 4 from REG_MODEM_CONFIG2
 config = config | 0b10000000; // sets bit 7 from REG_MODEM_CONFIG2
 break;
 case SF_9: config = config & 0b10011111; // clears bits 6, 5 & 4 from REG_MODEM_CONFIG2
 config = config | 0b10010000; // sets bits 7 & 4 from REG_MODEM_CONFIG2
 break;
 case SF_10: config = config & 0b10101111; // clears bits 6 & 4 from REG_MODEM_CONFIG2
 config = config | 0b10100000; // sets bits 7 & 5 from REG_MODEM_CONFIG2
 break;
 case SF_11: config = config & 0b10111111; // clears bit 6 from REG_MODEM_CONFIG2
 config = config | 0b10110000; // sets bits 7, 5 & 4 from REG_MODEM_CONFIG2
 //getBW();
 uint8_t bw;
 bw=LORA_Read_Register(RegModemCfg1)>>4;
 if( bw == BW_125)
 { // LowDataRateOptimize (Mandatory with SF_11 if BW_125)
 config1=LORA_Read_Register(RegModemCfg3);
 config1 = config1 | 0b00001000;
 LORA_Write_Register(RegModemCfg3,config1);
 }
 break;
 case SF_12: config = config & 0b11001111; // clears bits 5 & 4 from REG_MODEM_CONFIG2
 config = config | 0b11000000; // sets bits 7 & 6 from REG_MODEM_CONFIG2
 if( bandwidth == BW_125)
77
 { // LowDataRateOptimize (Mandatory with SF_12 if BW_125)
 config1=LORA_Read_Register(RegModemCfg3);
 config1 = config1 | 0b00001000;
 LORA_Write_Register(RegModemCfg3,config1);
 }
 break;
 }
 // Check if it is neccesary to set special settings for SF=6
 if( spFactor == SF_6 )
 {
 // header OFF with SF=6 (Implicit mode)
 LORA_Implicit_Header();
 LORA_Write_Register(RegDetectionOptimize, 0xc5);
 LORA_Write_Register(RegDetectionThreshold, 0x0c);
 }
 else
 {
 LORA_Explicit_Header();
 LORA_Write_Register(RegDetectionOptimize, 0xc3);
 LORA_Write_Register(RegDetectionThreshold, 0x0a);
 }
 // set the AgcAutoOn in bit 2 of REG_MODEM_CONFIG3
 config1 = (LORA_Read_Register(RegModemCfg3));
 config1=config1 | 0b00000100;
 LORA_Write_Register(RegModemCfg3,config1);
 // write the new SF
 LORA_Write_Register(RegModemCfg2, config); // Update config2
 DELAY_Ms(100);
 /*Check the update*/
 config1=LORA_Read_Register(RegModemCfg2);
 while(config1!=config);
 //Go back to previous state
 LORA_Write_Register(RegOpMode, state);
}
/*
* Set Signal Bandwidth of LoRa module
* */
void LORA_Set_Signal_BW(uint16_t BW){
 int8_t state;
 uint8_t config,config1;
 //uint16_t level;
 bandwidth=BW;
 /*Save current module state*/
 state=LORA_Read_Register(RegOpMode);
 LORA_Set_Lora_Mode();
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 config=LORA_Read_Register(RegModemCfg1);
 config = config & 0b00001111; // clears bits 7 - 4 from
RegModemCfg1
 switch(BW)
 {
 case BW_125:
 // 0111
 config = config | 0b01110000;
 uint8_t spreading_factor;
 spreading_factor=LORA_Get_Spreading_Factor();
 if( spreading_factor == 11 || spreading_factor == 12)
 { // LowDataRateOptimize (Mandatory with BW_125 if SF_11 or
SF_12)
 config1=LORA_Read_Register(RegModemCfg3);
 config1 = config1 | 0b00001000;
 LORA_Write_Register(RegModemCfg3,config1);
 }
 break;
 case BW_250:
 // 1000
 config = config | 0b10000000;
 break;
 case BW_500:
 // 1001
 config = config | 0b10010000;
 break;
 }
 LORA_Write_Register(RegModemCfg1,config); // Update config1
 DELAY_Ms(100);
 config1=LORA_Read_Register(RegModemCfg1);
 while(config1!=config);
 LORA_Write_Register(RegOpMode, state); // Getting back to
previous status
 DELAY_Ms(100);
}
/*
* Set LoRa module coding rate
* */
void LORA_Set_Coding_Rate(uint16_t d){
 int8_t config,config1;
 uint8_t state;
 state=LORA_Read_Register(RegOpMode);
 LORA_Set_Lora_Mode();
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 config = LORA_Read_Register(RegModemCfg1);
 config = config & 0b11110001; // clears bits 3 - 1 from
REG_MODEM_CONFIG1
 switch(d)
 {
 case CR_5:
 config = config | 0b00000010;
 break;
 case CR_6:
 config = config | 0b00000100;
 break;
 case CR_7:
 config = config | 0b00000110;
 break;
 case CR_8:
 config = config | 0b00001000;
 break;
 }
 LORA_Write_Register(RegModemCfg1, config);
 DELAY_Ms(100);
 config1 = LORA_Read_Register(RegModemCfg1);
 while(config!=config1);
 LORA_Write_Register(RegOpMode, state);
 DELAY_Ms(100);
}
/*
* Set LoRa preamble length
* */
void LORA_Set_Preamble_Length(uint32_t preamble_length){
 LORA_Write_Register(RegPreambleMsb, (uint8_t)(preamble_length >>8));
 LORA_Write_Register(RegPreambleLsb, (uint8_t)(preamble_length >>0));
}
/*
*
* Set Sync Word*/
void LORA_Set_Sync_Word(uint8_t sync_word){
 LORA_Write_Register(RegSyncWord, sync_word);
}
/*
* Set CRC
* */
void LORA_Set_CRC(uint8_t crc){
 if(crc){
 LORA_Write_Register(RegModemCfg2,
LORA_Read_Register(RegModemCfg2) | 0x04);
 while(!(LORA_Read_Register(RegModemCfg2) & 0x04));
 }
 else
 LORA_Write_Register(RegModemCfg2,
LORA_Read_Register(RegModemCfg2) & 0xfb);
}
/*
* Clear the flags of LoRa Module*/
void LORA_Clear_Flags(){
 uint8_t status;
 status=LORA_Read_Register(RegOpMode);
 if(modem==LORA){
 // LoRa mode
 LORA_Write_Register(RegOpMode, ModeLoraStandby); // Stdby mode to write in registers
 LORA_Write_Register(RegIrqFlags, 0xFF); // LoRa mode flags register
 LORA_Write_Register(RegOpMode, status); // Getting back to previous status
 }
 else{
 // FSK mode
 LORA_Write_Register(RegOpMode, ModeFskStandby); // Stdby
mode to write in registers
 LORA_Write_Register(RegIrqFlags1, 0xFF); // FSK mode flags1 register
 LORA_Write_Register(RegIrqFlags2, 0xFF); // FSK mode flags2 register
 LORA_Write_Register(RegOpMode, status); // Getting
 }
}
/*
* Put LoRa Module in Standby Mode
* */
void LORA_Standby_Mode(){
 LORA_Write_Register(RegOpMode, ModeLongRange | ModeStandby);
}
/*
* Begin sending packets over LoRa
* */
void LORA_Begin_Tranmission(uint8_t header){
 /*Put Module in Standby Mode*/
 LORA_Standby_Mode();
 if(header)
 LORA_Implicit_Header();
 else
 LORA_Explicit_Header();
 /*Reset payload length and buffer address*/
 LORA_Write_Register(RegFifoAddrPtr, 0);
 LORA_Write_Register(RegPayloadLength, 0);
}
/*
* End Transmission over LoRa
* */
void LORA_End_Transmission(){
 /*Put LoRa Module in Transmission Mode*/
 LORA_Write_Register(RegOpMode, ModeLongRange | ModeTx);
 /*Wait for Transmission to Complete*/
 while ((LORA_Read_Register(RegIrqFlags) & IrqMaskTxDone) == 0);
 /*Clear IRQs of the Module*/
 LORA_Write_Register(RegIrqFlags, IrqMaskTxDone);
}
/*
* Put Module in implicit header mode
* */
void LORA_Implicit_Header(){
 implicit_header_mode=1;
 LORA_Write_Register(RegModemCfg1, LORA_Read_Register(RegModemCfg1)
| 0x01);
}
/*
* Put Module in explicit header mode
* */
void LORA_Explicit_Header(){
 implicit_header_mode=0;
 LORA_Write_Register(RegModemCfg1, LORA_Read_Register(RegModemCfg1)
& 0xfe);
}
/*
* Send Byte Data over LoRa
82
* */
size_t LORA_Write(const uint8_t *buffer, size_t size){
 /*Get payload length*/
 uint16_t currentLength = LORA_Read_Register(RegPayloadLength);
 /*Check the size of payload*/
 if ((currentLength + size) > MaxPacketLength) {
 size = MaxPacketLength - currentLength;
 }
 /*Write payload to buffer*/
 size_t i ;
 for (i = 0; i < size; i++) {
 LORA_Write_Register(RegFifo, buffer[i]);
 }
 /*update payload length in the module register*/
 LORA_Write_Register(RegPayloadLength, currentLength + size);
 return size;
}
/*
* Send single byte over LoRa
* */
size_t LORA_Write_Byte(uint8_t byte){
 return LORA_Write(&byte, sizeof(byte));
}
/*
* Perform the Receiver chain calibration for LF and HF bands
* */
void LORA_Rx_Chain_Cal(){
 /* Cutoff the PA ,RFO output, power = -1 dBm*/
 LORA_Write_Register( RegPaConfig, 0x00 );
 /*Start Receiver chain calibration of LF band*/
 LORA_Write_Register( RegImageCal, ( LORA_Read_Register(
RegImageCal ) & RfImagecalMask ) | RfImagecalStart );
 while( ( LORA_Read_Register( RegImageCal ) & RfImagecalRunning )
== RfImagecalRunning );
 // Sets a Frequency in HF band
 LORA_Set_Frequency(0xD90000);//Channel 17 at 868MHz
 // Launch Rx chain calibration for HF band
 LORA_Write_Register( RegImageCal, ( LORA_Read_Register(
RegImageCal ) & RfImagecalMask ) | RfImagecalStart );
 while( ( LORA_Read_Register( RegImageCal ) & RfImagecalRunning )
== RfImagecalRunning );
}
/*
* Put the Module in LoRa Mode
* */
void LORA_Set_Lora_Mode(){
 uint8_t state;
 //i=0;
 do{
 DELAY_Ms(200);
 LORA_Write_Register(RegOpMode, ModeSleep); // Sleep mode (mandatory to set LoRa mode)
 LORA_Write_Register(RegOpMode, ModeLongRange); // LoRa sleep mode
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 //DELAY_Ms(50+i*10);
 state = LORA_Read_Register(RegOpMode);
 } while (state!=ModeLoraStandby); // LoRa standby mode  if(state==ModeLoraStandby)
 modem=LORA;
 else
 while(1);
}
/*
* Set Lora Mode according to libelium documentation
* Sets the proper badnwidth, spreading factor and
* coding rate of LoRa Modulation
*
* */
void LORA_Set_Mode(uint8_t libelium_mode){
 int8_t state;
 state=LORA_Read_Register(RegOpMode);
 uint8_t config,config1;
 if(modem == FSK)
 LORA_Set_Lora_Mode();
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 switch (libelium_mode)
 {
 /* mode 1 (better reach, medium time on air)*/
 case 1:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_12); // SF = 12
 LORA_Set_Signal_BW(BW_125); // BW = 125 KHz
 break;
 /* mode 2 (medium reach, less time on air)*/
 case 2:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_12); // SF = 12
 LORA_Set_Signal_BW(BW_250); // BW = 250 KHz
 break;
 /* mode 3 (worst reach, less time on air)*/
 case 3:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_10); // SF = 10
 LORA_Set_Signal_BW(BW_125); // BW = 125 KHz
 break;
 /* mode 4 (better reach, low time on air)*/
 case 4:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_12); // SF = 12
 LORA_Set_Signal_BW(BW_500); // BW = 500 KHz
 break;
 /* mode 5 (better reach, medium time on air)*/
 case 5:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_10); // SF = 10
 LORA_Set_Signal_BW(BW_250); // BW = 250 KHz
 break;
 /* mode 6 (better reach, worst time-on-air)*/
 case 6:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_11); // SF = 11
 LORA_Set_Signal_BW(BW_500); // BW = 500 KHz
 break;
 /* mode 7 (medium-high reach, medium-low time-on-air)*/
 case 7:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_9); // SF = 9
 LORA_Set_Signal_BW(BW_250); // BW = 250 KHz
 break;
 /* mode 8 (medium reach, medium time-on-air)*/
 case 8:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_9); // SF = 9
 LORA_Set_Signal_BW(BW_500); // BW = 500 KHz

 break;
 /* mode 9 (medium-low reach, medium-high time-on-air)*/
 case 9:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_8); // SF = 8
 LORA_Set_Signal_BW(BW_500); // BW = 500 KHz
 break;
 /* mode 10 (worst reach, less time_on_air)*/
 case 10:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_7); // SF = 7
 LORA_Set_Signal_BW(BW_500); // BW = 500 KHz
 break;
 /* test for LoRaWAN channel*/
 case 11:
 LORA_Set_Coding_Rate(CR_5); // CR = 4/5
 LORA_Set_Spreading_Factor(SF_12); // SF = 12
 LORA_Set_Signal_BW(BW_125); // BW = 125 KHz
 // set the sync word to the LoRaWAN sync word which is 0x34
 LORA_Set_Sync_Word(0x34);
 break;
 default: while(1); // The indicated mode doesn't exist
 };
 if(libelium_mode==1){
 config=LORA_Read_Register(RegModemCfg1);
 config1=LORA_Read_Register(RegModemCfg2);
 while(!((config>>1)==0x39)||!((config1>>4)==SF_12));
 }
 LORA_Set_Sync_Word(0x12);
 LORA_Write_Register(RegOpMode, state); // Getting back to previous status
 DELAY_Ms(100);
}
/*
* Set Address of the LoRa Node
* Address should be from 1-255
* Address one is usually the gateway
*
86
* */
void LORA_Set_Node_Address(uint8_t addr){
 node_address=addr;
 uint8_t status;
 status=LORA_Read_Register(RegOpMode);
 if(modem==LORA){
 /*Allow access to FSK registers in LoRa Mode*/
 LORA_Write_Register(RegOpMode,LoraStandbyFskRegMode);
 }
 else{
 /*Put module in standby mode*/
 LORA_Write_Register(RegOpMode,ModeFskStandby);
 }
 /* Write node and broadcast addresses to Registers*/
 LORA_Write_Register(RegNodeAddr, addr);
 LORA_Write_Register(RegBroadcastAddr, BroadcastAddr);
 DELAY_Ms(100);
 /*Restore Node status*/
 LORA_Write_Register(RegOpMode,status);
}
/*
* Get Current Spreading Factor from the Module
* */
uint8_t LORA_Get_Spreading_Factor(){
 //int8_t state;
 if(modem==FSK)
 while(1); /*Spreading factor not available in FSK mode*/
 return LORA_Read_Register(RegModemCfg2)>>4;
}
/*
* Dump Registers of the LoRa Module
* */
void LORA_Dump_Registers(){
 uint8_t i,x;
 for (i = 128; i==0 ; i--) {
 x= LORA_Read_Register(i);
 printf("\nRegister %x = %x",i,x);
 }
}
/*
* Set Packet Type
* */
void LORA_Set_Packet_Type(uint8_t type){
 packet_sent.type=type;
 if (type & Packet_Flag_Ack)
87
 requestAck=1;
}
/*
* LoRa send packet
* */
void LORA_Send_Packet(uint8_t dest, char *payload,uint8_t length){
 uint8_t state;
 state=LORA_Read_Register(RegOpMode);
 LORA_Clear_Flags();
 if (modem==LORA){
 LORA_Write_Register(RegOpMode, ModeLoraStandby);
 }
 else
 LORA_Write_Register(RegOpMode, ModeFskStandby);
 destination=dest;
 packet_sent.dst=dest;
 packet_sent.src=node_address;
 packet_sent.packnum=packetNumber;
 packetNumber++;
 //packet_sent.retries=0;
 payloadlength=length+4;
 if((modem==FSK)&& payloadlength>MaxPayloadFsk)
 payloadlength = MaxPayloadFsk;
 uint8_t i;
 //for(i = 0; i < payloadlength; i++){
 packet_sent.data = payload; // Storing payload in packet structure //}
 LORA_Write_Register(RegPayloadLength,payloadlength);
 uint8_t length_set=0;
 length_set=LORA_Read_Register(RegPayloadLength);
 while(length_set!=payloadlength);
 LORA_Write_Register(RegFifoAddrPtr,0x80);
 /*Write Packet to FIFO*/
 LORA_Write_Register(RegFifo,packet_sent.dst);
 LORA_Write_Register(RegFifo,packet_sent.type);
 LORA_Write_Register(RegFifo,packet_sent.src);
 LORA_Write_Register(RegFifo,packet_sent.packnum);
 /*Write Data*/
 for(i = 0; i < payloadlength; i++){
 LORA_Write_Register(RegFifo,payload[i]);
 }
 /*Restore Mode*/
 LORA_Write_Register(RegOpMode, state);
 /*Transmit...may call end tramit funciton*/
 LORA_Write_Register(RegOpMode, LoraTxMode);
 /*Wait for Transmission to Complete*/
 while ((LORA_Read_Register(RegIrqFlags) & IrqMaskTxDone) == 0);
 /*Clear IRQs of the Module*/
 LORA_Write_Register(RegIrqFlags, IrqMaskTxDone);
}
/*
* Set Maximum Current of the module
* */
void LORA_Set_Max_Current(uint8_t current_rate){
 int8_t state=0;
 current_rate|= 0xb00100000;
 state=LORA_Read_Register(RegOpMode);
 if(modem==LORA)
 LORA_Write_Register(RegOpMode,ModeLoraStandby);
 else
 LORA_Write_Register(RegOpMode,ModeFskStandby);
 LORA_Write_Register(RegOcp,current_rate);
 LORA_Write_Register(RegOpMode,state);
}