In the MSP430x5xx and MSP430x6xx Family User's Guide (Literature Number: SLAU208P, June 2008–Revised October 2016), Section 32.2.7 Comp_B Port Disable Register CBCTL3 describes how analog signals applied to the CMOS GPIO inputs that share the Comparator B analog inputs can cause cross-conduction at the digital input stage when the analog voltage is near the CMOS gate's threshold voltage. The section goes on to describe how one should set the "Port Disable" bits for those inputs that have analog signals applied to them rather then being used as GPIOs.
That's great for Comparator B and I understand that. But on the MSP430F5359, those same pins are also pin-multiplexed to the ADC12 peripheral and, for P6.6, P6.7, P7.6, and P7.7, potentially to the DAC12_A peripheral as well and these peripherals DO NOT have "Port Disable" bits.
So, if one is using P6.0 through P6.7 or P7.4 through P7.7 signal pins as analog inputs to the ADC12 peripheral or if one is using P6.6, P6.7, P7.6, or P7.7 as the DAC12_A outputs, should one be setting the respective Comparator B "Port Disable" bits so the GPIO receivers are disabled? And if that's true, that should probably be documented somewhere, for example, in the ADC12 and DAC12_A sections.
