Part Number: MSP430F5529
I am trying to configure msp430f5529(launchpad) as following
32768Hz ---> XT1 ---> ACLK
4MHz ---> XT2 ---> FLL + DCO --> 24MHz ---> SMCLK, MCLK
I am getting DCO Fault below is my code ;
// Set Vcore to 3
PMM_setVCore(PMM_CORE_LEVEL_3);
initPorts(); // Config all the GPIOS (output low)
//////////////////////// use XT1 32768 Hz ////////////////////////////////////////////
P5SEL |= BIT4 + BIT5; // Select XT1
UCSCTL6 &= ~XT1OFF; // Enable XT1
UCSCTL6 |= XCAP_3; // Internal load cap
//////////////////////// use XT2 4.0 MHz ////////////////////////////////////////////
P5SEL |= BIT2 + BIT3; // Select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT2
__bis_SR_register(SCG0 + SCG1); // Disable the FLL control loop
UCSCTL3 |= SELREF__XT2CLK; // FLLref = XT2
UCSCTL0 = 0;
UCSCTL1 = DCORSEL_5;
UCSCTL2 = FLLD_1 + 5; // DCO= 24MHz, FLLREF= 4MHz(XT2)
__bic_SR_register(SCG0 + SCG1); // enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 24 MHz / 4MHz = 6144 = MCLK cycles for DCO to settle
__delay_cycles(6144);
do // Loop until XT1 and XT2 stabilize
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2, XT1, DCO, FLL fault flags
SFRIFG1 &= ~OFIFG; // Clear oscillator fault flag
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT2DRIVE0 + XT2DRIVE1); // Decrease XT2 Drive as it is stabilized
UCSCTL6 &= ~(XT1DRIVE0 + XT1DRIVE1); // Decrease XT1 Drive as it is stabilized
// UCSCTL4 |= SELA__XT1CLK + SELS__XT2CLK + SELM__XT2CLK; // ACLK = XT1, MCLK = SMCLK = XT2
UCSCTL4 |= SELA__XT1CLK + SELS__DCOCLK + SELM__DCOCLK; // ACLK = XT1, MCLK = SMCLK = DCO
