- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Hi,
I am having some trouble with the eUSCI of the MSP430FR2100 in SPI mode.
The code below is a simplified version of the example "msp430fr211x_eusci_spi_standard_slave.c" with added support for the "MSP430FR4133 LaunchPad Development Kit".
(MSP430Ware_3_80_04_05/examples/devices/MSP430FR2xx_4xx/MSP430FR21xx_MSP430FR2000_Code_Examples/C/msp430fr211x_eusci_spi_standard_slave.c)
As seen in the interrupt routine each received char is simply written to the transmit register unless the value is 0xAA in which case 0x00 is written.
Placing an interrupt at line 136 "if (uca0_rx_val == 0xAA)" and running the code on the MSP430FR4133 works as expected.
However when the code is run on the MSP430FR2100 the break-point in the interrupt routine is only hit for every 8th char received. Also the transmitted char is shifted as seen below:
root@host:~# spidev_test -D /dev/spidev0.0 -H -O -s 1000 -v -p "\x10"
spi mode: 0x3
bits per word: 8
max speed: 1000 Hz (1 KHz)
TX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
RX | 01 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
root@host:~# spidev_test -D /dev/spidev0.0 -H -O -s 1000 -v -p "\x10"
spi mode: 0x3
bits per word: 8
max speed: 1000 Hz (1 KHz)
TX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
RX | 02 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
root@host:~# spidev_test -D /dev/spidev0.0 -H -O -s 1000 -v -p "\x10"
spi mode: 0x3
bits per word: 8
max speed: 1000 Hz (1 KHz)
TX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
RX | 04 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
root@host:~# spidev_test -D /dev/spidev0.0 -H -O -s 1000 -v -p "\x10"
spi mode: 0x3
bits per word: 8
max speed: 1000 Hz (1 KHz)
TX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
RX | 08 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
root@host:~# spidev_test -D /dev/spidev0.0 -H -O -s 1000 -v -p "\x10"
spi mode: 0x3
bits per word: 8
max speed: 1000 Hz (1 KHz)
TX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
RX | 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .
Does anybody have an idea about what is going on here and how to solve this issue.
Best regards,
Anders
//******************************************************************************
// MSP430FR211x Demo - eUSCI_A0, SPI 4-Wire Slave multiple byte RX/TX
//
// Description: SPI master communicates to SPI slave sending and receiving
// 3 different messages of different length. SPI slave will enter LPM0
// while waiting for the messages to be sent/receiving using SPI interrupt.
// ACLK = NA, MCLK = SMCLK = DCO 16MHz.
//
//
// MSP430FR2111
// -----------------
// /|\ | RST |<- Master's GPIO (To reset slave)
// | | |
// ---|RST P1.7|<- Data In (UCA0SIMO)
// | |
// | P1.6|-> Data Out (UCA0SOMI)
// | |
// | P1.5|<- Serial Clock In (UCA0CLK)
// | |
// | P1.4|<- Master's GPIO (UCA0STE)
//
// Nima Eskandari and Ryan Meredith
// Texas Instruments Inc.
// February 2018
// Built with CCS V7.3
//******************************************************************************
#include <msp430.h>
#include <stdint.h>
#include <stdbool.h>
//******************************************************************************
// Device Initialization *******************************************************
//******************************************************************************
void initSPI()
{
#ifdef __MSP430FR4133__
UCB0CTLW0 = UCSWRST; // **Put state machine in reset**
UCB0CTLW0 |= UCCKPL | UCMSB | UCSYNC | UCMODE_2; // 4-pin, 8-bit SPI Slave
UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCB0IE |= UCRXIE; // Enable USCI0 RX interrupt
#else
//Clock Polarity: The inactive state is high
//MSB First, 8-bit, Master, 4-pin mode, Synchronous
UCA0CTLW0 = UCSWRST; // **Put state machine in reset**
UCA0CTLW0 |= UCCKPL | UCMSB | UCSYNC | UCMODE_2; // 4-pin, 8-bit SPI Slave
UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI0 RX interrupt
#endif
}
void initGPIO()
{
// Configure GPIO
#ifdef __MSP430FR4133__
P5SEL0 |= BIT0 | BIT1 | BIT2 | BIT3;
#else
P1SEL0 |= BIT4 | BIT5 | BIT6 | BIT7; // Configure SPI pins
#endif
// P1SEL1 = 0x00;
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
}
void initClockTo16MHz()
{
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // set to fDCOCLKDIV = (FLLN + 1)*(fFLLREFCLK/n)
// = (487 + 1)*(32.768 kHz/1)
// = 16 MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked
}
//******************************************************************************
// Main ************************************************************************
// Enters LPM0 and waits for SPI interrupts. The data sent from the master is *
// then interpreted and the device will respond accordingly *
//******************************************************************************
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
initClockTo16MHz();
initGPIO();
initSPI();
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
__no_operation();
return 0;
}
//******************************************************************************
// SPI Interrupt ***************************************************************
//******************************************************************************
#ifdef __MSP430FR4133__
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#else
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#endif
{
uint8_t uca0_rx_val = 0;
#ifdef __MSP430FR4133__
switch(__even_in_range(UCB0IV, USCI_SPI_UCTXIFG))
#else
switch(__even_in_range(UCA0IV, USCI_SPI_UCTXIFG))
#endif
{
case USCI_NONE: break;
case USCI_SPI_UCRXIFG:
#ifdef __MSP430FR4133__
uca0_rx_val = UCB0RXBUF;
UCB0IFG &= ~UCRXIFG;
#else
uca0_rx_val = UCA0RXBUF;
UCA0IFG &= ~UCRXIFG;
#endif
if (uca0_rx_val == 0xAA)
uca0_rx_val = 0x00;
#ifdef __MSP430FR4133__
while (!(UCB0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
UCB0TXBUF = uca0_rx_val;
#else
while (!(UCA0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = uca0_rx_val;
#endif
break;
case USCI_SPI_UCTXIFG:
break;
default:
break;
}
}
Screenshot of Saleae logic data capture using SPI mode 0x0 (UCCKPL = 0, UCCKPH = 1). Only interrupt for every 8th char on the MSP430FR2100.
Could it be a problem that the clock is running after the CS is deasserted?
Here is the Saleae logic analyzer output from the MSP430FR4133 setup that is using an RPI and spidev_test as the master. Notice that on the MSP430FR2100 test setup above there is 9 clock periods and only 8 on the MSP430FR4133 setup. Could this be the cause of only getting an USCI_SPI_UCRXIFG interrupt for every 8th char received?
**Attention** This is a public forum
