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MSP430F67791A: customizing MSP430Fxxx Flash based custom UART BSL

Arun Raj38
Prodigy 150 points
Part Number: MSP430F67791A
Other Parts Discussed in Thread: MSP430F6736A

hi,
currently we are working on a project based on msp430f67791A and msp430f6736A in which we have to develop a bootloader (on both controllers) so that we could update the firmware over the air using UART interface. we found this "customizing the MSP BSL". we searched the Userguide provided, but couldnt find any reference on how to change the target controller using any of the examples given in the firmware package. im not that much familiar with any of the TI's microcontrollers. (but i need to finish this project anyway). in the IAR_BSL_Source folder, i could not find an example for msp430f6xx series..

  • 0
    TI__Genius 10860 points

    Hi Arun,

    did you have a look at our MSPBSL web page?

    Please especially have a look at STEP 3: Customizing the MSP BSL if not done so yet.

    The Custom BSL documentation hopefully helps (did you have a look at the Application Report?).

    Changing the Target Controller will have to be done in your IDE, IAR in your case. You'd have to adapt the project settings.

    If possible, please state where exactly you're currently stuck at so that we can better guide you to the right documentation or give an explanation.

    Thanks and best regards,

    Britta

  • 0 in reply to Britta Ruelander
    Prodigy 150 points

    thanks for the reply...

    i downloaded MSP430BSL_1_00_12_00 and opened MSP430F552x_TA_UART.eww.

    Britta Ruelander said:
    Changing the Target Controller will have to be done in your IDE, IAR in your case. You'd have to adapt the project settings.

    by this did you mean navigating to Project->Options->General Options->Target(tab)->Device->MSP430F67791A ?

    ok, i did that. ( i dont know if i opened the correct workspace coz i didnt find one for MSP430F6xxx ). if i'm right, my project is compiling without error, but with warnings...

    Building configuration: MSP430F552x_TA_UART - Debug
    Updating build tree...
     
    10  file(s) deleted.
    Updating build tree...
    BSL430_API.c BSL430_Command_Interpreter.c BSL430_PI_TA.c  
    Warning[Pa050]: non-native end of line sequence detected (this diagnostic is only issued once) E:\ARUN\CODES\MSP Bootloader\MSP430BSL_1_00_12_00\5xx_6xx_BSL_Source\MSP430F552x_TA_UART\BSL_Device_File.h 1
    Warning[Pe1105]: #warning directive: DEBUG BUILD! E:\ARUN\CODES\MSP Bootloader\MSP430BSL_1_00_12_00\5xx_6xx_BSL_Source\Command_Interpreter\BSL430_Command_Interpreter.c 137
    BSL430_Low_Level_Init.s43
    Warning[409]: Jcc or JMP at end of segment part could possibly trigger hardware problem CPU40, as anything could be placed immediately next to it, including the problematic values 0x0?40 and 0x0?50 E:\ARUN\CODES\MSP Bootloader\MSP430BSL_1_00_12_00\5xx_6xx_BSL_Source\MSP430F552x_TA_UART\BSL430_Low_Level_Init.s43 107

    Linking
    Warning[w12]: Using SFB/SFE in banked or packed segment CODE_ID in module ?cstart ( C:\Program Files\IAR Systems\Embedded Workbench 7.3\430\lib\dlib\dl430xlsfn.r43 )
    Warning[w12]: Using SFB/SFE in banked or packed segment CODE_ID in module ?cstart ( C:\Program Files\IAR Systems\Embedded Workbench 7.3\430\lib\dlib\dl430xlsfn.r43 )
    Warning[w12]: Using SFB/SFE in banked or packed segment CODE_ID in module ?cstart ( C:\Program Files\IAR Systems\Embedded Workbench 7.3\430\lib\dlib\dl430xlsfn.r43 )
    Warning[w12]: Using SFB/SFE in banked or packed segment CODE_ID in module ?cstart ( C:\Program Files\IAR Systems\Embedded Workbench 7.3\430\lib\dlib\dl430xlsfn.r43 )
     
    Total number of errors: 0
    Total number of warnings: 7

    are these warnings normal?

  • 0 in reply to Arun Raj38
    TI__Genius 10860 points
    Hi Arun,

    I've asked one of our experts to look into this so please allow some time to further investigate the behavior you see.
    I'll come back to you latest mid next week.
    Thanks for your patience,
    Britta
  • 0 in reply to Arun Raj38
    TI__Intellectual 2460 points

    Hi Arun,

    I checked the explanation of SFB stands for "Segment Begin" and SFE for the "Segment End". When we build the BSL in MSP430F5x we have to be careful that the JTAG signature also lies on the BSL are 0x17FC-0x17FF. We need to make sure that if we want JTAG still accessible, we need to keep the value on this region 0xFF or 0x00.

    The warning comes as in the device memory map, there is a "JtagLockKey" section at 0x17FC-0x17FF, while in the BSL linker command file it is defined the BSL memory area is located -Z(CODE)ZAREA_CODE=1010-17FF. The warning reminds us about the overlapping of these two section.

    You can generate any binary format (TI TXT for example), see what is compiled under this area. as long it is the condition you intend to have, then you can ignore the warning.

    Let me know if this helps you to understand the warning.

  • 0 in reply to Fatmawati_Santosa
    TI__Genius 10860 points
    Hi Arun,

    do you have further questions regarding this answer that Fatma posted? If not, please select "Resolved" for the post that solved your issue so this thread can be closed out. If you have a different question, please select "Ask a related question" or " Ask a new question".
    Thanks a lot!

    Best regards,
    Britta

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