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MSP430FR5959: MSP430FR5959

Anushka Parab21
Intellectual 700 points
Part Number: MSP430FR5959

Dear sir,

We are using MSP430FR5959 for our prroject. Our instrument is multichannel analyzer with one master and
4 slave unit(data logger). All board uses MSP430 chip.

We are using code composer studio( Version: 8.1.0.00011 ) for our softare development and programming.


During course of our development cycle we observed follwing problems in hardware.
1) After completing of software , we kept 5 instruments under observation for coninuous 8 hours a day.
We observed that after about ten days our instrument it fail to work after power on. We doubted Master MCU
board. We tested it.
We found supply voltage 3.3 to MCU Vcc pin-4/ DGND(pin 33) were o.k.(3.3 VDC). We suspect MCU chip
failure. We reprogrammed the MSP chip and our instrument started working. The reason for failure was
not known.
This failure can again occur. So please guide us.
During development cycle this problem has occured many times but we were suspecting software bug.
But we also obsevre that out of 5 instrument only 2 are giving this problem. Other 3 are working non stop.

regards,

anushka parab

  • 0
    Guru 26200 points
    I join this thread to be a bystander.
    However, do you use external clock sources like LFXTCLK or HFXTCLK?
    Do you monitor clock faults?
  • 0 in reply to Tomasz Kocon
    Intellectual 700 points
    we are using following clock setting

    FRCTL0 = FRCTLPW | NWAITS_1;
    // Clock System Setup
    CSCTL0_H = CSKEY >> 8; // Unlock CS registers
    CSCTL1 = DCORSEL | DCOFSEL_4; // Set DCO to 16MHz
    CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK; // Set SMCLK = MCLK = DCO,
    // ACLK = VLOCLK
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
    CSCTL0_H = 0; // Lock CS registers

    and we dont know about clock fault and its usage.if is this the problem then can u please explain us in details ??
  • 0 in reply to Anushka Parab21
    Guru 26200 points
    I understand that you do not use any external oscillator.

    DCOCLK has 3.5% tollerance (except a settling time after wake up and a frequency change).
    VLOCLK can bee in range from 6.0 to 14.0 kHz.
    Does your 1 master and 4 slaves software architecture tolerates so different clock differences?
  • 0 in reply to Tomasz Kocon
    Intellectual 700 points

    ya we used internal clock set as 16MHz

    and  out of 5 devices , only particulate devices will fail to execute code on it. and the same code working fine with other devices. 

     

  • 0 in reply to Anushka Parab21
    Guru 26200 points
    I have no idea, nor resources to help you.
  • 0 in reply to Tomasz Kocon
    TI__Mastermind 40890 points
    Hello Anushka,

    Are you still experiencing this issue?

    Have you tested the "bad" IC on a "good" board and vice versa? This could help determine if this is an IC or board problem. Also, can you provide a schematic?

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