MSP430F5510: SLAA514 : reference schematics

I'm using a quartz with 12pF of Cl, but sometime doesn't start to oscillate at 4MHz, XT2IN remains at DC level of 300mV and XT2OUT is zero. The packege used is RGC for MSP430F5510 device 

The pad P5.4 and P5.5 are floating (refered to Crystal XT1 input), are there some external device issue to do to have the P5.2/XT2IN PAD in high impedence (SLAS645J, paragraph 6.11.6), in order to feed the XT2IN to Unified Clock System ?

tizzoni adamo said:

I'm using a quartz with 12pF of Cl, but sometime doesn't start to oscillate at 4MHz, XT2IN remains at DC level of 300mV and XT2OUT is zero. The packege used is RGC for MSP430F5510 device 

The pad P5.4 and P5.5 are floating (refered to Crystal XT1 input), are there some external device issue to do to have the P5.2/XT2IN PAD in high impedence (SLAS645J, paragraph 6.11.6), in order to feed the XT2IN to Unified Clock System ?

I'm sorry, but I don't understand what you're asking. Also, this question seems to be different than your original question. For new questions, we recommend that you start a new thread. I don't know if you're confusing XT1 and XT2 or asking how to set up the pins to use XT1 or XT2. On the firmware side, have you referenced the code examples for this device yet?

MSP430F55xx_UCS_08.c

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//******************************************************************************
//  MSP430F552x Demo - XT2 sources MCLK & SMCLK
//
//  Description: This program demonstrates using XT2 to source MCLK. XT1 is not
//  connected in this case.
//
//  By default, LFXT1 is requested by the following modules:
//     - FLL
//     - ACLK
//  If LFXT1 is NOT used and if the user does not change the source modules,
//  it causes the XT1xxOFIFG flag to be set because it is constantly looking
//  for LFXT1. OFIFG, global oscillator fault flag, will always be set if LFXT1
//  is set. Hence, it is important to ensure LFXT1 is no longer being sourced
//  if LFXT1 is NOT used.
//  MCLK = XT2
//
//               MSP430F552x
//             -----------------
//        /|\ |                 |
//         |  |                 |
//         ---|RST              |
//            |            XT2IN|-
//            |                 | HF XTAL (455kHz - 16MHz)
//            |           XT2OUT|-
//            |                 |
//            |             P7.7|--> MCLK = XT2
//            |             P2.2|--> SMCLK = XT2
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   April 2009
//   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************

#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

  P2DIR |= BIT2;                            // SMCLK set out to pins
  P2SEL |= BIT2;                            
  P7DIR |= BIT7;                            // MCLK set out to pins
  P7SEL |= BIT7;
  
  P5SEL |= BIT2+BIT3;                       // Port select XT2

  UCSCTL6 &= ~XT2OFF;                       // Enable XT2 
  UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                            // Since LFXT1 is not used,
                                            // sourcing FLL with LFXT1 can cause
                                            // XT1OFFG flag to set
  UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO

  // Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  UCSCTL6 &= ~XT2DRIVE0;                    // Decrease XT2 Drive according to
                                            // expected frequency
  UCSCTL4 |= SELS_5 + SELM_5;               // SMCLK=MCLK=XT2

  while(1);                                 // Loop in place
}

Regards,

James