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CCS/MSP430F5528: Can't capture uart receive interruption

Part Number: MSP430F5528

Tool/software: Code Composer Studio

Hi, I am using tdc1000-tdc7200evm to communicate with other board through uart from GPIO3\GPIO4. I can read from the oscilloscope that there is data transmitted, and I connect RX TX with a wire. However, the program cannot jump into RX interrupt.  I found the interrupt enable register was 0 but I enabled interruptions in my code.

By the way, I have enabled system interruptions.

Here are my codes and the value of UART registers:

void InitUART(void){

  UCAxCTL1 |= UCSWRST;                      // **Stops USCI state machine**

  UART_PxREN &= ~(UART_TX_PAD|UART_RX_PAD); //Disable port pull resistors
  UART_PxDIR &= ~UART_RX_PAD;               // Configure P4.5 as input
  UART_PxDIR |= UART_TX_PAD;                // Configure P4.4 as output
  UART_PxSEL |= (UART_TX_PAD|UART_RX_PAD);  // Px.x & Px.X = USCI_Ax TXD & RXD

  UCAxCTL0 = 0x00;                          // No parity, 8-N-1 mode
  UCAxCTL1 |= UCSSEL__ACLK;                 // Select 12MHz ACLK as clock source for the UART
  UCAxBR = UART_BAUDRATE_REG;               // defines baudrate
  UCAxMCTL =  (UCBRF_0|UCBRS_1);          // Modulation UCBRSx = 1 //vishy: 115200  baudrate selection @ 12MHz
//  UCAxMCTL =  (UCBRF_0|UCBRS_0);            // Modulation UCBRSx = 1 //vishy: 230400  baudrate selection @ 12MHz
  UCAxIFG &= ~UCAxRXIFG;          //Clear RX IFG  (Interrupt flag register)
  UCAxIFG &= ~UCAxTXIFG;          //Clear TX IFG  (Interrupt flag register)
  UCAxIE |= UCAxRXIE +UCAxTXIE;             // Enable USCI_A1 RX interrupt
  UCAxCTL1 &= ~UCSWRST;           // **Initialize USCI state machine**


}
#pragma vector=UCAxRX_VECTOR;
__interrupt void receiveUART(void)
{
unsigned short i;
unsigned char TimeOutCounter = 0;

if (UCAxRXIFG)// USCI_A0 RX buffer ready?
{
open_flag=UCAxRXBUF;

} //wait until Tx buffer is empty
UartRx_flag = 1;

}

What can I do?

  • > UCAxIE |= UCAxRXIE +UCAxTXIE; // Enable USCI_A1 RX interrupt
    > UCAxCTL1 &= ~UCSWRST; // **Initialize USCI state machine**

    The IE bits can't be set while the USCI is in reset. Reverse the order of those statements:

    > UCAxCTL1 &= ~UCSWRST; // **Initialize USCI state machine**
    > UCAxIE |= UCAxRXIE +UCAxTXIE; // Enable USCI_A1 RX interrupt

    Unsolicited: Keep in mind that the TXIFG will be set at the moment you set the TXIE. I don't see any provision for that in your ISR.
  • Thank you so much, it helps a lot!

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