Other Parts Discussed in Thread: DAC161S055, LM4120
Thank you very much for your kind reply.Now, I have generated PWW signal and I can see on oscilloscope. I have couple of questions more. Please guide me.
1) is there any formula to calculate timer period in Up mode configuration and duty cycle for PWM??
2) how can I calculate the sampling frequency ?? I am calculating it as SMCLK/(2^16-1)=(48e6/65535) and theoretical answer is 732 Hz but on oscilloscope I am just getting 45.9 Hz.
3) how can I synchronize the rising edge of PMW with Sample and hold of ADC and falling edge with conversion ??
I am going to attached my code also for your further consideration.
Many many thanks for your kind help. I am sorry if I am asking some basic questions also.
const Timer_A_UpModeConfig upModeConfig =
{
TIMER_A_CLOCKSOURCE_SMCLK, // Timer initialization by SMCLK Clock Source
TIMER_A_CLOCKSOURCE_DIVIDER_1, // ACLK/1 = ACLK=32KHz
65535, // Timer Period (2^15)
TIMER_A_TAIE_INTERRUPT_ENABLE, // Enable Timer ISR
TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE, // Enable Interrupt CCR0
TIMER_A_DO_CLEAR // Clear Counter
};
/* Timer_A Compare Configuration Parameter */
const Timer_A_CompareModeConfig compareConfig =
{
TIMER_A_CAPTURECOMPARE_REGISTER_1, // Compare and Capture register CCR1
TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE, // Disable CCR interrupt
TIMER_A_OUTPUTMODE_RESET_SET, // Compare Output Mode 7
8192 // Compare Value 8192 Period (2^13)
};
/* Timer_A PMW Configuration Parameter */
Timer_A_PWMConfig pwmConfig =
{
TIMER_A_CLOCKSOURCE_SMCLK,
TIMER_A_CLOCKSOURCE_DIVIDER_1,
65535, // Timer Period (2^15)
TIMER_A_CAPTURECOMPARE_REGISTER_1,
TIMER_A_OUTPUTMODE_RESET_SET, // Compare Output Mode 7
8192 // duty cycle 25%
};
