Part Number: MSP432P401R
Hi,
I am working on MSP432P401R and DAC161S055EVM. As per some given guidlines here by senior memebers, I am able to set up SPI communication between MSP432 and DAC161s055. As given Timing diagram in script, I am getting perfect waveforms but I am facing a very strange issue at this moments.
According to DAC161 data sheet (page 7) and MSp technical reference manual (page 940), waveforms of MOSI and SOMI should have shape (symmetry) when CS and CLK are runing and I have attached the reference image below from data sheet of DAC.
My problem is that , In my case when I was checking the waveforms for SCLK, CS, MOSI and SIMO. In the presence of SCLK (if I am attaching measurement probe to CLK pin), MOSI and SOMI waveforms are not symmetrical any more. MOSI has perfect diagram but SOMI has different shape and then DAC output remain at zero (idle position).
But when I do not measure the SCLK then the SOMI and MOSI have symmetrical shape and DAC analog output updates also as according to given digital input. (How I observed this CLK issue ,just accidently removed SCLK probe and I figured out this observation ).
I think, I have problem somewhere with the clock frequency of SPI protocol because I am providing SMCLK to SPI configuration protocol and it has 24 MHZ but bit clock generator of SPI can have maximum 20M Hz frequncy.
As per given SPI protocol information(block diagram 935 and page939 ) , bit clock frequency can be calculated but I am not understanding where should I apply this bit clock frequency and how pre divder will have impact to reduce SMCLK frequency.
Please help me out from this issue.
Many thanks for your kind help and for every sugesstion.