Part Number: MSP430FR6047
There is the following paragraph in the user's manual
22.2.4 Data Transfer Controller (DTC) and Internal Data Buffer
The SDHS supports output data rates up to 8 Msps, which is faster than the system DMA can support, so
the SDHS has a dedicated Data Transfer Controller (DTC) and an internal data buffer to support up to 8-
MHz data transfer speed to the target memory.
Figure 22-14 shows the block diagram of the output data path. A conversion result from digital filter goes
first to the internal data buffer. The buffer has 64-word depth. As soon as a new data is available in the
buffer, the data is latched with the system clock (called synchronization to the system clock) and is written
to SDHSDT register. Then the DTC reads the data from SDHSDT register and transfers to the destination
memory location.
The DTC may require more than one sample period to transfer the data to system memory. Thus, the
buffer depth is selected to achieve the 8-MHz data transfer speed when the system clock is equal to or
higher than the SDHS output data rate. Take care when selecting SDHSCTL1.OSR bits or the system
clock frequency. The system clock frequency must be equal to or greater than the SDHS output data rate,
or a data overflow may occur.
System clock frequency ≥ SDHS output data rate
SDHS output data rate = PLL output frequency / SDHSCTL1.OSR
Question:
How to understand System clock frequency?
System clock frequency means MCLK or SMCLK or something else.
If I use DTC or CPU to read the data from SDHSDT register, are there any differences in frequency settings between MCLK and SMCLK?
Is Internal Data Buffer a FIFO buffer?
If I don't read SDHSDT register, will the newly generated data be in the buffer (when there are less than 64 16bits data in the buffer) instead of in SDHSDT register?
