CCS/MSP430FR2355: CCS/MSP430FR2355

i am new to the msp430fr2355 launchpad and  have a problems related to program related to UART-

#define MCLK_FREQ_MHZ 8 // MCLK = 8MHz

__delay_cycles((unsigned int)3000 * MCLK_FREQ_MHZ);

// Wait FLL lock status (FLLUNLOCK) to be stable
// Suggest to wait 24 cycles of divided FLL reference clock

#define MCLK_FREQ_MHZ 1 // MCLK = 1MHz

__delay_cycles((unsigned int)3000 * MCLK_FREQ_MHZ);

// Wait FLL lock status (FLLUNLOCK) to be stable
// Suggest to wait 24 cycles of divided FLL reference clock

What will  delays in both case and how would we calculate delays in both situations?

Even we are using different frequency for MCLK then how in both above cases it is producing same delay for 24 cycles only.

View online

You received th