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MSP430F5359: Are "Constant Generator" accesses really not "Register Mode" operands?

Atlant Schmidt
Expert 1715 points
Part Number: MSP430F5359

Folks:

I'm using IAR's icc430 C compiler and its inline assembler. I've noticed that this tool flags
the following sorts of instructions as ineligible for "RPT" (repeat) operations because the
tool thinks that the accesses to the Constant Generator registers (R2 and R3) aren't
"Register Mode" operands.

0018 4E53   ADDX.A #0x0, R14    // Src: R3/CG2 in mode 0, Dst: R14 in mode 0
0018 5E53   ADDX.A #0x1, R14    // Src: R3/CG2 in mode 1, Dst: R14 in mode 0
0018 6E53   ADDX.A #0x2, R14    // Src: R3/CG2 in mode 2, Dst: R14 in mode 0
0018 6E52   ADDX.A #0x4, R14    // Src: R2/SR/CG1 in mode 2, Dst: R14 in mode 0
0018 7E52   ADDX.A #0x8, R14    // Src: R2/SR/CG1 in mode 3, Dst: R14 in mode 0
0018 7E53   ADDX.A #0x-1, R14   // Src: R3/CG2 in mode 3, Dst: R14 in mode 0

(The error printout is included below)

Is it really true that using the Constant Generators makes the instruction ineligible
for being repeated or is IAR being excessively restrictive here?

Atlant

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

Compiling: hello.cpp --> hello.r43

asm( "ADDX.A #0, R14" ); // :
^
"hello.cpp",543 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

asm( "ADDX.A #1, R14" ); // :
^
"hello.cpp",546 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

asm( "ADDX.A #2, R14" ); // :
^
"hello.cpp",549 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

asm( "ADDX.A #4, R14" ); // :
^
"hello.cpp",552 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

asm( "ADDX.A #8, R14" ); // :
^
"hello.cpp",555 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

asm( "ADDX.A #-1, R14" ); // :
^
"hello.cpp",558 Error[Og006]: Error in inline assembly: "Error[459]: Repeated instruction must have register mode operand(s)"

  • 0
    Guru 316920 points
    I cannot find such a restriction in the CPU documentation.

    If you generate the machine code by hand, is it executed correctly?
  • 0 in reply to Clemens Ladisch
    Expert 1715 points

    Clemens:

    > I cannot find such a restriction in the CPU documentation.

    Thanks -- I concur!

    > If you generate the machine code by hand, is it executed correctly?

    That was going to be my next step. I'll try it now and report back.

    Atlant

  • 0 in reply to Atlant Schmidt
    Expert 1715 points

    > > If you generate the machine code by hand, is it executed correctly?

    > That was going to be my next step. I'll try it now and report back.

    I couldn't figure out how to coerce IAR to produce arbitrary hex opcodes but I COULD edit the produced load file so I conducted the experiment with both an immediate (#n) repeat count and a register supplying the repeat count. As it turns out, in all cases, the IAR compiler is correct: If you specify the Constant Generator registers as the source registers, the Extension Word that would ordinarily call for repeating the operation is IGNORED. The operation proceeds normally, but only once.

    I guess I'd still like to hear TI state that this is the expected behavior (for all MSP430X processors) but other than that, this question is resolved. And I guess I'll submit a documentation bug to TI about the fact that this behavior isn't documented; they could be more clear about exactly what counts as "Register Mode" operands.

    Atlant

  • 0 in reply to Atlant Schmidt
    TI__Genius 17960 points
    Hi Atlant,
    we're sorry for the inconvenience you've experienced.
    Please let me clarify the situation. The CG with CPUX -X commands still is a register operation. But with the -X version of the instruction, the register operations take one cycle more. Thus e.g. ADD R13,R14 needs one cycle, like ADD #01h,R14, but ADDX R13,R14 likewise ADDX #01h,R14 needs 2 CPU cycles. So also with the extended address range instructions the CG saves you one CPU cycle.

    Best regards
    Peter

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