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CCS/MSP432P401R: MSP432P401R receiving fault state when is configuring the clock

Part Number: MSP432P401R


Tool/software: Code Composer Studio

Hello everybody.

I'm trying to interface IMU-9250 and MSP432 (through I2C) and I got a source code from GitHub to serve as a start point.
I made some modifications because the code got some errors when the code was compiled.

Now, when the code is running on MSP432, it always is calling the 'faultISR' function:

/* This is the code that gets called when the processor receives a fault        */
/* interrupt.  This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger.                                               */
static void faultISR(void)
{
    /* Enter an infinite loop. */
    while(1)
    {
    }
}

I'd like to know if somebody faced this error before and whether could solve it.
I guess that is something wrong with the clock setup because I had some issues setting the 42MHz without configuring the VCORE correctly.

Thank you so much guys!

main code:

#include "msp.h"
#include "IMU/I2Cdev.h"
//#include "IMU/MPU6050_6Axis_MotionApps20.h"
#include "IMU/MPU6050.h"
#include <stdio.h>
#include "UART/UART_A0.h"
#include <stdint.h>

/*
 extern "C"
 {
 #include "msp432_startup_ccs.c"
 }

 8*/

MPU6050 accelgyro;
I2Cdev i2cdev;
UART_A0 uartA0;

char debugOutput[50];
int16_t ax, ay, az;
int16_t gx, gy, gz;

void MPU9150_setupCompass();
void VCORE1();

//void eUSCIB0IsrHandler(void);



//SETA O NIVEL DE TENSAO PARA VCORE 1 (PARA USAR EM 48MHZ)
void VCORE1()
{
    while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
    PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR__AM_LDO_VCORE1;
    while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
}

void main(void)
{
    WDTCTL = WDTPW | WDTHOLD;           // Stop watchdog timer

    P6DIR |= BIT0;                          // P6.0 set as output
    P6OUT &= ~BIT0;

    VCORE1();

    CS->KEY = CS_KEY_VAL;
    CS->CTL0 = 0;
    CS->CTL0 = CS_CTL0_DCORSEL_5; // here you change the DCO frecuency, read MSP432P4xx Family Technical Reference Manual page 307
    CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;
    CS->KEY = 0;

    /*
    CS->KEY = CS_KEY_VAL;//0x695A; // unlock CS registers
    CS->CTL0 = 0; // reset DCO settings
    CS->CTL0 = CS_CTL0_DCORSEL_4; // select DCO 5 (48MHz)
    CS->CTL1 = CS_CTL1_SELA__REFOCLK | CS_CTL1_SELS__DCOCLK | CS_CTL1_SELM__DCOCLK; // ACLK = REFOCLK, SMCLK = MCLK = DCOCLK
    CS->KEY = 0; // lock CS registers
    */

    __enable_interrupt();
    NVIC_EnableIRQ(EUSCIB0_IRQn);// Enable eUSCIB0 interrupt in NVIC module

    //NVIC->ISER[0];
    //NVIC_ISER0 = 1 << ((INT_EUSCIB0 - 16) & 31); // Enable eUSCIB0 interrupt in NVIC module

    i2cdev.writeByte(0x68, 0x6B, 0);	//wake from sleep
    MPU9150_setupCompass();

    //accelgyro.initialize();
    //accelgyro.testConnection();
    //accelgyro.setIntDataReadyEnabled(1);

    while (1)
    {
        P6OUT |= BIT0;
        P6OUT &= ~BIT0;
        int i;
        for (i = 10000; i > 0; i--)
        {
            __no_operation();
        }
        //accelgyro.getMotion6(&ax, &ay, &az, &gx, &gy, &gz);
        i2cdev.writeByte(0x68, 0x6B, 0);	//wake from sleep
        //accelgyro.getAccelerationX();

        int n = sprintf(
                debugOutput,
                "ax: %d\t ay: %d\t az: %d\t gx: %d\t gy: %d\t gz: %6d\t", ax,
                ay, az, gx, gy, gz);

        uartA0.sendString(debugOutput);
        //accelgyro.getIntStatus();

    }

}

void MPU9150_setupCompass()
{
    /*
     //UCB0CTLW0 |= UCSWRST;
     UCB0I2CSA = MAG_I2C_ADDRESS;      //change Adress to Compass
     //UCB0CTLW0 &= ~UCSWRST;

     i2cdev.writeByte(0x68, 0x0A, 0x00); //PowerDownMode
     i2cdev.writeByte(0x68, 0x0A, 0x0F); //SelfTest
     i2cdev.writeByte(0x68, 0x0A, 0x00); //PowerDownMode
     */

    //UCB0CTLW0 |= UCSWRST;
    UCB0I2CSA = ACCEL_GYRO_I2C_ADDRESS
    ;      //change Adress to Compass
    //UCB0CTLW0 &= ~UCSWRST;

    i2cdev.writeByte(0x68, 0x24, 0x40); //Wait for Data at Slave0
    i2cdev.writeByte(0x68, 0x25, 0x8C); //Set i2c address at slave0 at 0x0C
    i2cdev.writeByte(0x68, 0x26, 0x02); //Set where reading at slave 0 starts
    i2cdev.writeByte(0x68, 0x27, 0x88); //set offset at start reading and enable
    i2cdev.writeByte(0x68, 0x28, 0x0C); //set i2c address at slv1 at 0x0C
    i2cdev.writeByte(0x68, 0x29, 0x0A); //Set where reading at slave 1 starts
    i2cdev.writeByte(0x68, 0x2A, 0x81); //Enable at set length to 1
    i2cdev.writeByte(0x68, 0x64, 0x01); //overvride register
    i2cdev.writeByte(0x68, 0x67, 0x03); //set delay rate
    i2cdev.writeByte(0x68, 0x01, 0x80);

    i2cdev.writeByte(0x68, 0x34, 0x04); //set i2c slv4 delay
    i2cdev.writeByte(0x68, 0x64, 0x00); //override register
    i2cdev.writeByte(0x68, 0x6A, 0x00); //clear usr setting
    i2cdev.writeByte(0x68, 0x64, 0x01); //override register
    i2cdev.writeByte(0x68, 0x6A, 0x20); //enable master i2c mode
    i2cdev.writeByte(0x68, 0x34, 0x13); //disable slv4
}

  • I don't see where you set wait states (=1) in FLCTL_BANK[0/1]_RDCTL. Per data sheet (SLAS826G) sec. 5.8, this is required above 24MHz. I'm pretty sure one of the Examples suite shows how to do this.
  • Please refer to the example here:

    dev.ti.com/.../

    Regards,
    Chris
  • That is right Bruce, I didn't configure the Flash wait-state. I used the example code, that Chris has sent in another answer, and worked fine. Now I have another errors to solve :D

    Thank you so much for the quick answer.

    part of modified main code:

    void main(void)
    {
        volatile uint32_t i;
        
        uint32_t currentPowerState;
    
        WDT_A->CTL = WDT_A_CTL_PW |
                     WDT_A_CTL_HOLD;            // Stop WDT
    
        P1->DIR |= BIT0;                        // P1.0 set as output
    
        /* NOTE: This example assumes the default power state is AM0_LDO.
         * Refer to  msp432p401x_pcm_0x code examples for more complete PCM
         * operations to exercise various power state transitions between active
         * modes.
         */
    
        /* Step 1: Transition to VCORE Level 1: AM0_LDO --> AM1_LDO */
    
        /* Get current power state, if it's not AM0_LDO, error out */
        currentPowerState = PCM->CTL0 & PCM_CTL0_CPM_MASK;
        if (currentPowerState != PCM_CTL0_CPM_0)
            error();
    
        while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
        PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
        while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
        if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
            error();                            // Error if transition was not successful
        if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_1)
            error();                            // Error if device is not in AM1_LDO mode
    
        /* Step 2: Configure Flash wait-state to 1 for both banks 0 & 1 */
        FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) |
                FLCTL_BANK0_RDCTL_WAIT_1;
        FLCTL->BANK1_RDCTL  = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK)) |
                FLCTL_BANK1_RDCTL_WAIT_1;
    
        /* Step 3: Configure DCO to 48MHz, ensure MCLK uses DCO as source*/
        CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access
        CS->CTL0 = 0;                           // Reset tuning parameters
        CS->CTL0 = CS_CTL0_DCORSEL_5;           // Set DCO to 48MHz
        /* Select MCLK = DCO, no divider */
        CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) |
                CS_CTL1_SELM_3;
        CS->KEY = 0;                            // Lock CS module from unintended accesses
        __enable_interrupt();
    

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