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MSP430G2553: Timer1 never enters A0 ISR

Part Number: MSP430G2553

I am trying to set up the Timer1 on my MSP, but I just can not figure out what the cause of my problems is.

I wrote a test program to see the Timer1 work. The program starts the Timer1 by pressing S2 over an ISR. Then the Timer is supposed to switch On and Off two LEDs with different frequencies.

My problems:

1. the ISR for CCR0 of Timer1 is never called and the REDLED always stays off.

2. The GREEN LED turns on, but does not turn off when S2 is pressed.

Can anyone help me with that?

#include<msp430g2553.h>

int mspON = 0;

void configClocks(void){
     BCSCTL1 = CALBC1_1MHZ;                    // Set range
     DCOCTL = CALDCO_1MHZ;                     // Set DCO step + modulation
     BCSCTL3 |= LFXT1S_2;                      // LFXT1 = VLO
     IFG1 &= ~OFIFG;                           // Clear OSCFault flag
     BCSCTL2 = SELM_0;                         // MCLK = DCO = 1MHz - SMLCK = MCLK --> clocks are same, so that UART is sourced from SCLK and matches the example
}

//is stopped, MC_x must be set to continuous mode --> TA1CTL |= MC_2
void configTimerA1(void){
    TA1CTL = TASSEL_2 + ID_3 + MC_0 + TAIE;       //SMLOCK 1MHZ - input Divider 8 - MC Timer is in stop

    TA1CCR0 = 1250;
    TA1CCTL0 = 0;

    TA1CCR1 = 27500;           
    TA1CCTL1 = 0;

}

void main(void)
{
    WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

    configClocks();
    configTimerA1();

    P1DIR |= 0xF7;      // Set P1.0 to output direction
    P1OUT = 0;          // LED1 on
    P1IE |= BIT3;       // P1.3 interrupt enabled
    P1IES |= BIT3;      // P1.3 Hi/lo edge
    P1IFG &= ~BIT3;     // P1.3 IFG cleared
    P1OUT |= BIT3;
    P1REN |= BIT3;

    _BIS_SR(GIE); // Enter LPM4 w/interrupt

    while(1){}
}

// Port 1 interrupt service routine
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
    if(mspON){
        mspON = 0;
        TA1CTL &= ~MC_3;
    }
    else{
        mspON = 1;
        TA1CTL |= MC_2;
    }
    P1IFG &= ~BIT3; // P1.3 IFG cleared
}

#pragma vector=TIMER1_A0_VECTOR
__interrupt void Timer_A1 (void)
{
    TA1CCR0 += 1250;
    P1OUT ^= BIT0;
}

// TIMER1 -> access to timer A1; A1 access to CCR1
#pragma vector=TIMER1_A1_VECTOR
__interrupt void Timer_A1_1 (void)
{
    TA1CCR1 += 27500;
    P1OUT ^= BIT6;

    TA1CCTL1 &= ~CCIFG;
}

  • Seems like I have found a solution to my problem myself.

    First in the TAxCCTLx registers the interrupts must be enabled.

    Second in the ISR Timer1_A1 the overflow flag has to be cleared when overflow occurred.

  • I suspect this is what you just said, but I'll say it anyway: TAIE corresponds with TAIFG, and CCIE corresponds with CCIFG. Except for CCTL0:CCIFG, any/all need to be explicitly reset.

    The TA1IV can make this a little easier, though it will impose its own order on simultaneous events.

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