MSP430G2553: Maximum input frequency for ACLK?

Hello, Is this for a professional project or for otherwise?

If the latter, here is something that you may find useful:
forum.43oh.com/.../

Essentially, the 12 MHz off the LP USB chip is directed to the MSP. See the code - it confirms the clock works before it proceeds. ( while(IFG1 & OFIFG) )

BCSCTL3 = LFXT1S0 | LFXT1S1; // - Set XT1 clock type as external
do { // - Wait for MSP430 to detect clock is stable
IFG1 &= ~OFIFG; // Clear OFIFG
n = 250; while(--n); // Wait a while
} while(IFG1 & OFIFG); // Loop until OFIFG remains cleared
BCSCTL2 = SELM1 | SELM0 | SELS; // - Use LFXT1CLK as clock source


I have not personally done this. I can confirm, however, that the 2553 P1.0 in CLKIN mode operates faster than the specified 16 MHz at 3.3Vdd; evidence that the part is conservatively specified.

Hope this helps.

The table on Data Sheet (SLAS735J) p. 32 says (1) 32kHz [no range given] (2) <= 50kHz. Given (2) I suppose it's possible that (1) could also go to 50kHz, but I don't know that I'd bet my project on it.

Thanks for the response. Certainly it is interesting to see the MCLK sourced off the LXFT at a ridiculously high input frequency, but I was more wondering about using a higher frequency ACLK signal.

Your final comment indicates that it may be possible to source a timing clock input faster than 16MHz through the TA0CLK input?

My final purpose in the ACLK question was to look for a precise shared timing clock for recording pulses. I was hoping to use ACLK and only run 1 timing line per chip but it is looking more like I should run 2 lines per chip (1 for each TACLK)

Hi, that's why I asked if it was a professional project, or a casual one.    If professional, then LFXT1 is sub-50KHz per spec.

1...   the link I provided showed a 'hobby type' hack to get 12MHz into LFXT1 - thus giving high speed to MCLK *and* certainly ACLK. Fig 5.1 of x2xx Family UG shows this routing. Clearly, this is 'use at own risk' !   I tried it once some years ago after reading that note, and it worked. It's handy if the project is on a Launchpad.

2...   I hope I'm not leading you astray on '2553  P1.0.  This can be configured to be a high speed, on-spec clock input to TA0. A crystal derived clock for instance. See data sheet Table 16: DIR=0, SEL=1, SEL2=0.   I have used this input for 2 things:    to count high frequencies in the MHz range (using 32KHx xtal on P2.6/7 as the time base) ;    as input provided by an xtal osc to provide accurate TA0 interrupt timing, and TA0 CCR outputs. I've used 10.0, 13.0 and 16.384 MHz in to TA0CLK / P1.0.

Of course, P1.0 can source ACLK, but then it can't take in TA0CLK of course.

Don't know if this helps.