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MSP430F149: Character Received on SPI MOSI (in slave mode) clocking data in 1 cycle early (shift data to the right)

Part Number: MSP430F149


Hello,

I have my MSP430 in 4-pin slave mode and am trying to receive a character. However, the data I receive seems to be one bit shifted to the right. When I transmit 0x13 (0001 0011), the RXBUF reads 0x09 (0000 1001). As can be seen, a '0' is introduced as the MSB and the '1' LSB has been dropped. When I observe the oscilloscope (seen below) I see that transmitted signal is correct and can see where the phantom '0' character is coming from. I have the polarity and phase shift set to CKPH=0 and CKPL=1 (which I have confirmed matches the master in firmware as well as from the oscilloscope). I have tested this with other signals as well, sending 0xE4 (1110 0100) and receiving either 0xF2 (1111 0010) or 0x72 (0111 0010), depending on what the initial state of MOSI is. I have checked and the STE pin goes low ~3.7us before the clock signal is sent from the master.

Additionally, when I send the 0x13 again, it is captured correctly. (ie. first time 0x13 sent, 0x09 received. Second time 0x13 sent, 0x13 received)

How can I ensure the MSP is not capturing the signal early?

  • I found the issue. The power to the master device is controlled via the MSP. When the master is powered, there is about a 0.5sec delay between when master takes control of the SPI. When the master takes control of the SPI, the clock signal goes from low to high. Since the STE signal on the MSP does not completely stop the Receive Shift Register, the shift register detects this as a rising edge and samples the first bit. This results in only 7 bits left in the Receiver Shift Register before it is shifted to the RXBUF.
  • Beau,

    Glad to hear you found the issue!

    Best regards,

    Matt

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