MSP430FR5994: LEA to assist voice codec

Alexey,

There is a reference design created by TI named TIDM-FILTERING-SIGNALPROCESSING which showcases the performance of the Low Energy Accelerator (LEA) on MSP FRAM Microcontrollers in performing advanced filtering and signal processing. The LEA module provides the ability to perform real-time FIR filtering, implementation of a 256-point complex FFT, and provides high audio sampling rates of up to 20 kHz.

Hardware and software is available online for your reference.

Hopefully this helps point you in the right direction!

Best regards,

Matt

All publicly available documentation regarding LEA module is already reviewed by me. Hardware/electrical side is also not an issue. The question is strictly related to challenges of implementation voice codec with high compression ratio on MSP430 platform. Reference design you've mentioned is known to me and evaluated before. The issue is not in that domain.

Alexey,

Thank you for the clarification. There is an application report published by TI which explains doing speech and sound compression and decompression using the MSP430 MCU (SLAA361A), however this is not implemented using the LEA.

As it stands right now, there has not been any work done to accomplish any sort of voice encoding/decoding using the LEA on the MSP430 platform. Could you provide further detail on the existent narrowband voice compression codec you wish to implement? If it is not based on 2-bit ADPCM then what would your compression/decompression algorithm be based on? More importantly, what math computations would the algorithm require? If the required algorithms are computations that the MSP DSP Library + LEA supports then its implementation would seem doable.

Best regards,

Matt

Matt,

ADPCM codec uses simple CPU instruction set of commands, so no even multiplication is needed, therefore ADPCM can be easily implemented even on MSP430G series microcontrollers. However, human perceptibility of ADPCM coded signal is quite low due to high distortion-to-signal ratio and low compression ratio (1:4). The more complex algorithms based on CELP, ACELP, LPC and other methods require not only efficient multiplier module on CPU or coprocessor (best is MAC per 1,5 CPU cycle), but also support fast saturation arithmetic. Therefore, MSP430 is not suitable for such task. Cortex M4 is a good candidate. Actually some of such complex codecs can be implemented even in full duplex manner (MAC + saturation command set and high frequency speed fulfill requirements). I tested GSM-FR on Cortex-M4. It works well. But I really want an efficient solution based on FRAM devices range.

So, I want a 1:12 to 1:16 compression ratio in voice compression with perceivable level regardless of codec or method to use. Preferably using 11025-12000 sample rate (8000 sps actually has bad perception level).

Actually, I described more than needed. But I wanted to hear some of this from others. :)

Alexey

What capabilities of LEA module would l like to see? - Actually, fully accessible block operation on matrices or complex numbers using trigonometry and advanced math like SIN, COS, ASIN, ACOS, SQRT, TAN, CTAN, RMS, EXP, LOG, support of scalar math with saturation etc. All of them are supported by LEA internally, but are not available on command level to a programmer.

Matt,

This is a low priority request with expected implementation in some years. But, however, LEA module was introduced by TI in some months after I made a proposition in this E2E forum of adding a DSP to MSP430 platform. It was done unexpectedly good in terms power consumption, unfortunately, most of implementation made with blind layer and later most of capabilities were made unpublic.

Good news, historically Texas Instruments made big effort and resource investment in development of speech compression methods and codecs. The latest effort was done in consortium with other well known leading companies in development of speech codec, - ITU G.718. It exceeds my requirements in compression, but expected to consume too much CPU utilization up to ~80 MIPS of Cortex M4 for encoder and decoder individually. It is clearly not suited for TI's chips with 48MHz CPUs. 

Thanks for helping me resolve this issue,

Alexey