MSP430G2553: MSP430 - Are there RESET and TEST pin settings necessary for LPM4? Noting high sleep current

Chris Indo

Part Number: MSP430G2553

Hey all,

Thanks for reading. I've got a system using an MSP430G2553 chip and we are seeing high sleep currents. I am noticing that the TEST and RESET pins are not exactly VSS or VDD.

TEST is not connected to anything and RESET is externally pulled up using a 47K resistor (see below). We are seeing a high sleep current during LPM4. RESET is measuring about 14mV -below- VDD and TEST is measuring about 4mV above GND. I don't know if they are to blame for the high sleep current.

The datasheets don't mention anything about specific settings for RESET and TEST before going to LPM4. Do any of you have experience with this odd issue?

We are using TEST and RESET to program the MSP through Spy-By-Wire.

Thanks!

over 6 years ago

0 Eddie LaCost over 6 years ago

TI__Mastermind 43730 points

Hello Chris,

TEST and RST do not need to be configured specifically for going to LPM. If you were using the TEST pin for other functionality too, you would want to set this before sleep, but I understand you are not using it for anything else.

0 Chris Indo over 6 years ago in reply to Eddie LaCost

Intellectual 300 points

Hey Eddie.

If using TEST/RST for SBW, is there anything special that has to be done? Maybe some Gang programmer setting? (see below)

Does the pull-up resistance on RESET seem correct? 47K?

Thank you very much for your fast response.

-Chris

0 Eddie LaCost over 6 years ago in reply to Chris Indo

TI__Mastermind 43730 points

Chris,

The final target action is just a task that will run after the programming is complete. Typically, a reset is used to start running the application. There is not anything special that needs to be done with these pins.

The 47k pull up is correct. Typically, we also have a capacitor on the RST line as well. This is mostly for filtering to ensure false RST are not occurring from noise. I don't think this capacitor would impact the LPM current, but it is good practice. The schematic of the G2553 Launchpad board is below and shows the 47k and 1000pF on RST.

http://www.ti.com/lit/ug/slau772/slau772.pdf

0 Chris Indo over 6 years ago in reply to Eddie LaCost

Intellectual 300 points

Hi Eddie,
Thanks again. It seems like the issue isn't with RST and TEST pins.
However, one last thing - the voltage on the RST pin is always ~20mV below VCC. Is that normal?
With 20mV across the 47K pull-up resistor, that would imply that ~0.426uA is draining during LPM4 (which is supposed to only be 0.1uA)?

Thanks
Chris

0 Eddie LaCost over 6 years ago in reply to Chris Indo

TI__Mastermind 43730 points

Chris,

I would not expect that drop on the RST pin. Do you also have a capacitor on the RST line?

0 Jovi He over 6 years ago

TI__Intellectual 830 points

Hi Chris,

Would you please share the LPM4 high current value?

Best regards,
Jovi He

0 Chris Indo over 6 years ago in reply to Jovi He

Intellectual 300 points

Hi Jovi,

Thanks for the reply. The LPM4 current is usually above 10uA but RISES over time. Saw one unit that was as high as 800uA.

Thanks

Chris

0 Chris Indo over 6 years ago in reply to Eddie LaCost

Intellectual 300 points

Hi Eddie. Unfortunately we do not. Have you noticed before a leakage current issue when there is no cap on the RST line?

0 Jovi He over 6 years ago in reply to Chris Indo

TI__Intellectual 830 points

Chris,

10uA is much higher than the LPM4 idd, in LPM4 the clocks are shut down. Do you have any IO drive external load? The phenomenon the current RISES over time makes me thinking some IO are not initialized or there is leakage at the DVCC caps. would you please check that? Thank you.

Best regards,
Jovi He

0 Chris Indo over 6 years ago in reply to Jovi He

Intellectual 300 points

Hi Jovi,

For our system, a normal sleep current would be 3.4uA.. There is 0.1uA for the MSP chip and 3.3uA for peripherals. The extra load and rising current isn't from the peripherals.

Most of the I/Os are either at VCC and GND, so there would be no current leakage. The only I/Os not at VCC or GND are the RST and TEST pins; however, they aren't actually connected to anything besides ESD diodes (D12 and D13).

It is possible that there is leakage at the VCC cap (C3)., but we're not sure why that is so.

0 Jovi He over 6 years ago in reply to Chris Indo

TI__Intellectual 830 points

Chris,

Thanks for sharing the schametics. The TEST pin always has an pull down resistor inside the chip. RESET is pulled up here, I would not suspect these two pins cause the current leakage. Regarding the cap leakage, sometimes it happens, you can try to replace one to double-check.
What's the high current fail rate?

From the schmetics, I would suggest you:
1. Add an cap to the DVCC pin, TI recommended capacitor is 4.7uF (min) and typ. 10uF.
2. Check the OSC pins' waveform to see if any abnormal behavior there

Thanks,
Jovi He

0 Eddie LaCost over 6 years ago in reply to Chris Indo

TI__Mastermind 43730 points

Chris,

Is C3 the only capacitor on Vcc? If so, you also want to have some bulk capacitance, typically 1uF and 10uF. Check the G2553 launchpad for recommended values. I'm not sure that's related to your problem, but definitely recommended.

www.ti.com/.../msp-exp430g2et

**Attention** This is a public forum

MSP low-power microcontrollers

MSP low-power microcontroller forum

MSP430G2553: MSP430 - Are there RESET and TEST pin settings necessary for LPM4? Noting high sleep current