MSP430F4784: 16-bit sigma-delta ADC question

Hi Scott,

Thanks for posting your question to E2E! In short, the MSP430F4784 does not feature a notch filter for 50/60Hz rejection unfortunately.

The MSP430F4784's SD16_A module features a Sinc3 comb filter that performs the decimation on the  1-bit data stream from the modulator. Figure 29-3 and Section 29.2.7 in the MSP430x4xx Family User's Guide shows/discusses how the first notch of the filter is equal to the sampling frequency, Fs. Fs equals the modulation frequency, Fmod, divided by the oversampling rate (OSR). Thus, the notch can be placed by specifying the sampling frequency using Fmod and OSR. At the minimum Fmod and highest OSR, the minimum Fs equals approximately 117.9Hz. In Figure 29-3, the notches occur every integer multiple of Fs up to Fmod. As you can see, setting the first notch at 50Hz or 60Hz isn't possible with F4784.

Now, with the newer MSP430F6779A's SD24_B module, you can set Fs equal to 50Hz (Fmod = 50kHz, OSR = 1000) OR 60Hz (Fmod = 60kHz, OSR = 1000) but can't cover both at once like some of our other devices such as the ADS1248. The remaining notches would occur at 100Hz, 150Hz, etc. or 120Hz, 180Hz, etc. Ideally, a sampling frequency of 10Hz could be used which would mean notches at 50Hz AND 60Hz, but the MSP430F6779A can't achieve this slow sampling frequency unfortunately. At a higher level, this assumes sampling frequencies of either 50Hz or 60Hz is acceptable but I doubt it meets your sampling requirements.

Perhaps an alternative approach could be implementing a band-reject or stop band filter in software. Hope this helps!

Regards,

James