TI low power microcontroller

Hello Mudit,
is the PWM the only timing critical feature in your application? Do you have communications running in your application?
Which MSP430 derivative have you selected?

Best regards
Peter

Hi
Sorry for delayed response.

We are designing a on board charger for EV application . The control loop should be digital.In order to prevent limit cycling in the converter the sufficient condition :

1. The resolution of PWM should be min. 1 bit greater then ADC resolution(12 bit)

As my PWM frequency is 100khz ,the system clock to get the resolution of at least 14 bit PWM will be in GHz range,which is practically not feasible.In order to overcome the clock issue i am trying to implement 'PWM dithering ' to increase the resolution.

Can you tell me the procedure to implement in TI micro controller.

Reagrds
Mudit Mittal

Hello Mudit,
no problem.
So for the dithering you would have to switch between two neighbored PWM steps with a certain duty cycle. This could be 50/50, where you would switch between the steps with every PWM period, but you could also switch with different duty cycles to increase the resolution, like 1/3, 1/4. Basically you can implement any duty cycle you would like to have.
Now to the way, how to do that. As you probably know, usually a PWM is running without any CPU interaction, excluding the necessary initialization.
When changing the PWM duty cycle, you need to know, when to do so, to be able to perform it in a controlled way. This could be e.g. done by the Timer overflow interrupt, or the interrupt of the switching signal of the PWM. To do so, you need to enable the respective interrupt, the one or the other. In the respective interrupt service routine, you would need to perform the controlled change of the PWM.
What does it mean controlled? The Timer logic is with active PWM permanently comparing the CCRx register used for the PWM with the Timer value in the TAR register. Upon a match condition it executes the switching activity selected by the used PWM mode.
Now when updating the CCRx register with an active PWM, on the write access, especially in an asynchronous mode, means operating the CPU with an asynchronous clock relative to the Timer clock, erroneous compare match events could happen. This would result in an erroneous PWM duty cycle for the active period. Especially when permanently switching the CCRx settings, this would be very critical.

To avoid this, the PWM output state needs to be frozen before the update and re-activated afterwards. This can be done triggered by the previously mentioned interrupt, then switching the PWM mode (OUTMOD in TAxCCTLn) to the mode, where the output is controlled by the OUT bit in the TAxCCTLn register. Then do the update to the CCRx, clear potential IFGs and finally switch back to OUTMOD for the active PWM.

As you can see, this can keep your CPU quite busy, as you need to serve an interrupt each and every PWM period.

A potentially different option would be using the Timer_D in the MSP430F5172. This is a special high resolution timer with an integrated an calibrated by factory 256MHz oscillator. This would give you 11.x bit of a resolution with 100kHz. Not perfectly 12 bit as you would like to, but potentially a viable solution. Have you considered that one?

Best regards
Peter

Hi Peter

Thanks for the reply. After going through your post following are my queries

Assume i have system clock of 72 MHz and PWM frequency of 100Khz .the top value in the timer register will be
=72000000/100000
= 720-1
=719

The resolution form hardware will be greater then 9 bits but less then 10 bits.

As the system requires resolution of 12 bits .The extra PWM bits will come from dithering.

Assume my current duty cycle is 40% which corresponds to Value in Compare register be=((720*40)/100)-1,which corresponds to 287 in compare register of timer.

As the extra resolution need 8 clock cycles to increase the resolution .following are the set of combinations

[1,0,0,0,0,0,0,0],[1,0,1,0,1,0,1,0] etc




1.Shall i have to send duty cycle of 40% for 7 clock cycles and 41% for 1 clock cycles,is the logic is right?
2.If not how to select the duty cycle to increase the resolution.i.e if i send duty cycle of 40% what will be next value of duty cycle it will be 41% or 42% etc.
3.How to choose the set of combinations to implement the PWM dithering.e.g can it be [1,0,0,0,0,0,0,0] or[1,0,1,0,1,0,1,0]

Regards
Mudit Mittal

Hi Mudit,
maybe we should clarify first which device you're planning to use, to make sure, we're using the correct parameters, as e.g. no MSP430 can run with 72MHz.
Could you please clarify this point?

Best regards
Peter

Hi Peter

Sorry my bad its 50Mhz.

Regards

Mudit Mittal

Hi Mudit,
I am sorry, but there is also no MSP430 being able to operate at 50MHz.
The previously mentioned Timer_D in the MSP430F5172 is an exception, where only the Timer_D is able to operate with up to 250MHz, but the rest of the device is able to operate with up to 25MHz.
That's the maximum in the MSP430 portfolio.

Best regards
Peter

Hi Peter

The example which i posted is a generalized controller .I just to understand my approach of implementing the PWM dithering is right or not. I can tweak the resolution of PWM depending on Controller system frequency afterwards. Kindly help me out on that

Regards

Mudit Mittal