Part Number: MSP430FR2311
I'm not sure what is going on if it is my mistake or an issue with driverlib, but I cannot get the expected interrupt rate from the RTC. The code below gives me an interrupt period of 2ms. If I do the math 1/.002 = 500hz. 500hz *32000 = 16MHz. It seems like the clock to the RTC module isn't correct.
I also get a warning on RTC_clearInterrupt(RTC_BASE, RTC_CLOCKSOURCE_SMCLK); that says "#70-D integer conversion resulted in truncation"
*EDIT: As another datapoint I have a TimerB configured to interrupt at 128Hz with ACLK connected as its CLK source. I verified that it is running at 128Hz as expected.
int main(void) {
//Stop WDT
WDT_A_hold(WDT_A_BASE);
initClockTo16MHz();
/* Initialize peripherals */
initGPIO();
initRTC();
while(1)
{
}
}
void initGPIO(void){
// INPUT IS 0, OUTPUT is 1
//Set Px.x to output direction
P1DIR |= 0b00000000; // inputs
P2DIR |= 0b00001011;
P2OUT = 0x00;
PMM_enableTempSensor(); // enable temperature sensor
PMM_enableInternalReference();
// Select P2.0 as PWM Timer output function
P2SEL0 |= GPIO_PIN0;
P1SEL1 &= ~(BIT7); // USCI_A0 UART operation TX only
P1SEL0 |= BIT7;
// I2C pins
P1SEL0 |= BIT2 | BIT3;
P1SEL1 &= ~(BIT2 | BIT3);
//ADC Pins
P1SEL0 |= BIT0 | BIT1;
P1SEL1 |= BIT0 | BIT1;
/*
* Disable the GPIO power-on default high-impedance mode to activate
* previously configured port settings
*/
PMM_unlockLPM5();
}
void initClockTo16MHz()
{
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // set to fDCOCLKDIV = (FLLN + 1)*(fFLLREFCLK/n)
// = (487 + 1)*(32.768 kHz/1)
// = 16 MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked
CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;
}
// RTC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=RTC_VECTOR
__interrupt void RTC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(RTCIV,RTCIV_RTCIF))
{
case RTCIV_NONE: break; // No interrupt
case RTCIV_RTCIF: // RTC Overflow
P2OUT ^= BIT3;
//P2OUT &= ~BIT3;
//P2OUT |= BIT3;
break;
default: break;
}
}
void initRTC()
{
SYSCFG2 |= RTCCKSEL; // CONFIGURE TO USE ACLK INSTEAD OF SMCLK
RTC_init(RTC_BASE, 32000, RTC_CLOCKPREDIVIDER_1);
RTC_clearInterrupt(RTC_BASE, RTC_CLOCKSOURCE_SMCLK);
RTC_enableInterrupt(RTC_BASE, RTC_OVERFLOW_INTERRUPT);
RTC_start(RTC_BASE, RTC_CLOCKSOURCE_SMCLK);
}