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MSP430FR2355: Total sampling cycles of ADC

ytakano
Genius 9095 points
Part Number: MSP430FR2355


Hi,

Customer would like to know the way to calculate total sampling cycles of ADC.

ADC Configuration:

                     resolution : 12bit
      clock frequency (fADCCLK) : 4.4MHz
       conversion sequence mode : Repeat-sequence-of-channels
 sample-and-hold time (ADCSHTx) : 4 ADCCLK cycles
Input channel select (ADCINCHx) : 4 ch

       Sampling cycle :  4 clk
Synchronization cycle :  1 clk
     Conversion cycle : 14 clk

4 + 1 + 14 = 19 clk per one channel.
19clk * 4ch = 76clk per all 4 channels.

Q1. Is the calculation formula for 76 clock cycle  per all 4 channel correct?

Q2. How does ADC sample-and-hold time affect to the ADC result?

Regards,

  • 0
    TI__Mastermind 23395 points
    Q1: The calculation is correct.
    Q2: ADC sample-and-hold time (cycle) is set on ADCCTL0.ADCSHTx, the sample time should be equal or larger than tSample "Table 5-21. ADC, Timing Parameters" of DS to guarantee the sampling effect

    ADC sample-and-hold time (cycle) is set on ADCCTL0.ADCSHTx
    at the same time, the sample time should be equal or larger than tSample "Table 5-21. ADC, Timing Parameters" of DS.
    tSample is related with the external Equivalent C and R.
    In the DS, 0.61uS is given at the assumptive (normal) condition.
    In your case, the sample time = 4/4.4MHz = 0.91uS. it should be larger than 0.61uS.

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