MSP430 - UCS: How does the register DCORSEL needs to be if using FLL?

Thanks, Jens-Michael!

I think you took me back on the right road!

This is my example how I would chose relating to my project:

My source will be XT2 = 2²⁰Hz. My aim is to get the frequence for MCLK as high as possible.

Steps:

- Choosing the right range of frequency by DCORSEL (There the desired frequency must be between DCO₀ and DCO_max --> DORSEL=6 --> 10.7MHz ... 39.0MHz).

- Selecting the exact  frequency that is desired using FLL (n=1, N=2⁴, D=1, see formula mentioned above)  -->  f_DCOCLK = (2⁴+ 1) * 2²⁰Hz = 17.8MHz

- Check: ... Yes, f_DCOCLK is within the allowed range of  ACLK, SMCLK & MCLK.

Questions:

-  What are the maximums for MCLK, ACLK and SMCLK?  - I only found what is written on p.49 of the datasheet (SLAS590B), that MCLK can be up to 25MHz.

-  Does  f_DCOCLK has got a maximum?   -  Besides the point that it should fit to SMCLK, MCLK and ACLK (at least after using DIVS, DIVM or DIVA).

-  Is the use of FLLN in my calculation correct?

Thanks again Jens-Michael!

DORSEL6 would indeed be my first choice too - just the worst-case range isn't 10.7..39 but rather 12..35 if you omit DC=x = 0/31 :)

An alternative would be DOCRSEL7, going for 50MHz DCO and dividing by 2 (giving you 25MHz clock, since you wanted as fast as possible). It reduces the jitter introduced by the modulation.

The maximums of all clocks are 25MHz on this MSP. All peripherals working with a clock have a minimum pulse length of 20ns, which gives (for one high and low pulse per clock cycle) 40ns cycle length = 25MHz.

Bob Marley said:

Does  f_DCOCLK has got a maximum

DCOCLK is just the name of the digital signal that is output from the DCO circuit. So it has the same limitations (or capabilities) as the DCO itself. The usage of the DCO or OSC suffix is a bit spongy for historical reasons. What is a clock, what an oscillator... some peripherals accept clocks and oscillators as well (e.g. the WDT or the ADC), others convert oscillators into clocks, blah, blah, blah :)

p.s.: my datasheet revision is D and maybe there's already E (I don't use this processor anyway), so maybe you should update your library :)

Hello Jens-Michael, hello all other readers!

I think today I found a limitation for f_BCOCLK, but maybe I am wrong. I would be interested about what you will write.

Today I made some tests on the oscilloscope, trying to learn more about how the UCS works. Therefore I used the example code from TI.

Used example code:

   The program "MSP430F552x_tb_10.c" is creating PWM-signals on 3 different pins, using no ISR but hardware.

My changes in the code:

   By using this code I tried to find out how to show ACLK, SMCLK or MCLK as output on the related pins (e.g. P2.2 -> SMCLK or P7.7 -> MCLK).

   My CLK-Source should be XT1 (1MHz).

Results:

   At first I could not find any clock-signal on the oszilloscop but since I enabled MCLK, ACLK or SMCLK with SELA_5, SELM_5 or SELS_5 I found the right signal.

   As the code produces PWM-signals on different pins without enabling MCLK, ACLK or SMCLK (by SELA, SELM, SELS)

my converse argument is that

   if producing PWM-signals just by uC-hardware then there is no way to use the dividers DIVS, DIVM or DIVA which means that DCOCLK should not be too high.

Questions:

-  Is my conclusion right?   (converse agrument)

-  By the way: Can I damage the uC by using a too high CLK (e.g. DCOCLK)? - Because if not, then I don't need to ask about something like that any more and I could find it out on the  oscilloscope on myself.

Thanks again for your answer (and hints)!

-  On Monday I will do some further investigations.

I think you should take another look atht he description of the clock module in the users guide.

ACLK, MCLK and SMCLK are intermediate signals derived from a clock source and with a programmable divider.
The tiemr hardware is either sourced by ACLK, SMCLK or external, with an additional divider.
When producing PWM signals using the timer CCR registers, the PWM period is based on the CCR0 value as a coutn of tiemr ticks per PWM period. The timer ticks are based on a clock source (SMCLK or ACLK or external) divided by the ID setting. And SMCLK/ACLK are derived from an oscillator divided by the DIVA and DIVS settings (and DIVM for MCLK)
Oscillators for all three clocks may be VLO, REFO, LFXT1, XT2, DCO or DCODIV.

As a default, ACLK is sourced from XT1CLK (Which m,ay be 0Hz) and MCLK and SMCLK are driven by DCOCLKDIV. Your SELx_5 setting switched them to XT2, which is much higher. Anyway, MCLK and SMCLK do have a clock intially, yet it is a relatively slow one.
(Well, with MCLK not having a clock, your program wouldn't be executed at all).

Bob Marley said:

Can I damage the uC by using a too high CLK (e.g. DCOCLK)

BUT there is a chance for locking the device for JTAG usage: if your code executes and sets the clocks too high before the JTAG programmer can kick in, ther eis a chance that it will crash and not respond to JTAG anymore. It's rather unlikely for clock setting - the voltage supervisor can create such a situation easily, as it won't reset on a reset signal, only at power-on, but it is a possibility. In this case, usign the BSL will allow you to access it again, since the clock programming is reset on a reset signal and the BSL will kick in before your code is executes and crashes the device once more.

Hello Jens-Michael Gross,

(of course) you are right again! It is also written in the line in the code next to the last from where the clock signal comes from:

  TBCTL = TBSSEL_2+MC_1; // SMCLK, upmode

Thanks again for all your answers!!

PS: I will ask a new question within a new post so it will be easier for others to find for what they are looking for.