MSP430FR2433: Possible DriverLib bug in I2C set data rate

Hi lloyd,

The comments just reminds us what needs care during the clock configuration, although there is only one register for the frequency division setting besides the source selection, just as the UG description,

back to the real case of I2C, you can balance the clock source frequency setting(.i.e, flexible frequency setting of SMCLK) and prescaler setting so as to get the targeted frequency, hope this is helpful to you.

No, I am still confused.

My code initializes param->i2cClk= 1000000 and param->dataRate=EUSCI_B_I2C_SET_DATA_RATE_400KBPS. My intent is that the I2C bus data rate be 400kHz or less, which is the maximum supported by the two chips (the MSP430 and the slave) and my intent is that the clock source for the bitrate generator is SMCLK which is 1Mhz.  EUSCI_B_I2C_SET_DATA_RATE_400KBPS is defined in the .h as 400000.

The code in EUSCI_B_I2C_initMaster() seems to set UCBxBRW to 2 (integer division of 1,000,000/400,000 yields 2 since the fraction is truncated according to the C language.)

You cite that “The BITCLK frequency is given by: fBRCLK/UCBRx.” In my case, fBRCLK is 1Mhz and UCBRx is 2 (another name for the 16-bits of register UCBxBRW). That yields a BITCLK frequency of 500kHz, which is not my intent.

The cited text “The minimum high and low periods of the generated SCL are: tLOW,MIN = tHIGH,MIN = (UCBRx/2)/fBRCLK when UCBRx is even” applies since UCBRx IS even. It also yields tLOW,MIN and tHIGH,MIN both equal to 1/1,000,000. But that also means that the frequency (the number of high pulses per second) is 500kHz. (You can specify the frequency of a square wave in two ways, either as high pulses per second, or duration in seconds of each pulse. The cited text seems to redundantly specify the data rate both ways.)

I thought that the DriverLib implementation is hiding or abstracting some of the complexity of setting the data rate. I thought that choosing EUSCI_B_I2C_SET_DATA_RATE_400KBPS would yield 400kbps, but according to what you cited, it yields 500kbps.

Also, you cite “The maximum bit clock that can be used in single master mode is fBRCLK/4.” That seems to say that my intent is not supported, that if one chooses the SMCLK at 1Mhz, the eUSCI_B will only work at 250khz. It seems to imply that one can set UCBxBRW to a value such that the eUSCI_B won’t work. And that the DriverLib code does not protect you from doing that. It is strange, because my code seems to work (at 500kbps?) but I could just be lucky? I don’t really know the measured I2C SCL frequency since I don’t have a scope.

Since I don’t trust the DriverLib code, a workaround is to just set UCBxBRW myself. To value 4 which should yield a data rate of 250kbps.

Yes, if I don’t use the DriverLib function but write to the eUSCI_B registers directly, I can set the data rate properly.

Or, if I read the implementation of the DriverLib function, I will know to pass it “fudged” parameters, as you say: 2,000,000 and 5, and then it will set the data rate properly.

But my point is that if one just reads the API documentation of the DriverLib function, one might be misled.

In the code which you show above, (if SMCLK is 1Mhz) the data rate will be 500kbps (according to my math, don’t you agree?)

Which contradicts that you passed the value EUSCI_B_I2C_SET_DATA_RATE_400KBPS. The programmer thinks they are choosing 400kbps, but they get 500kbps.