MSP430FG6626: Is it possible for RTCAIFG flag to be set even when RTC interrupt is disabled?

Do you mind expanding into more detail when you say "when RTC interrupt is disabled"?

The RTCAIFG  event flag is enabled by configuring RTCAIE - as described below in section 1.2.6 of the MSP430x5xx and MSP430x6xx Family User's Guide:

"The user-programmable alarm event sources the real-time clock interrupt, RTCAIFG. Setting RTCAIE enables the interrupt. In addition to the user-programmable alarm, the RTC_C module provides for an interval alarm that sources real-time clock interrupt, RTCTEVIFG. The interval alarm can be selected to cause an alarm event when RTCMIN changed or RTCHOUR changed, every day at midnight (00:00:00) or every day at noon (12:00:00). The event is selectable with the RTCTEV bits. Setting the RTCTEVIE bit enables the interrupt."

-Chris

Thanks for the reply. We are trying to debug some unexpected behavior in the system, and one of the symptoms we observe is the RTCAIFG flag is set even though our firmware explicitly writes 0 to RTCAIE (interrupt disabled) during initialization and never sets that bit.

We have confirmed that the RTCAIFG bit is cleared when the system starts up, but eventually when we check again at a later time the RTCAIFG bit is set. We are trying to understand if there are any known logic paths that would allow the RTCAIFG flag to be set while the RTCAIE bit is not set? Or is this unexpected silicon behavior, possibly pointing to a H/W issue like the RTC16 erratum?

We are asking about RTC_B on MSP430FG6626 which is described in Chapter 22 of the User's Guide: http://www.ti.com/lit/slau208

Can you please explain the meaning of note (1) in Figure 23-2 of the User's Guide (excerpt below) ? The text in this note is ambiguous and confusing. Especially the part that says “but not the register bits itself; therefore, reconfiguration after wake-up from LPMx.5 before clearing LOCKLPM5 is required”.

Excerpt from User's Guide Section 23.3.1

The RTCAIFG will source the clock regardless if the interrupt RTCAIE is enabled. This is why you are seeing the behavior that you are experiencing with the RTCAIFG bit being set later. 

In regards to the datasheet comment under figure 1-4, the register bits themselves will be cleared during LPMx.5, but the original configuration will be saved. For example, if you have an alarm interrupt to configured to fire during LPMx.5 at a specific time, this configuration would be saved but the register itself will be cleared when entering LPMx.5.

-Chris

Chris,
I'm confused by the first sentence of your answer, "RTCAIFG will source the clock". The RTCAIFG is a flag bit in a register. What do you mean when you say it will source the clock? Please clarify further. Thanks