MSP430F5528: Sampling frequency of internal ADC

Hi,
unfortunately the ADC12_A of the MSP430F5528 runs with maximum 200ksps. This means it does not meet the sampling speed requirements for sampling a 2MHz signal. For this you would need at least a 4Msps ADC.

Best regards
Peter

Hi Peter：
But What about section 5.36 of the data table？It has a maximum of 5.0MHZ and 5.4MHZ
Can show that the sampling frequency can be this high?

Hi Timsen,
the 5MHz is the maximum clock of the ADC. The ADC needs like other digital clocked logic, like a CPU and other components also a clock to perform the operations, like conversion, switching of the multiplexers etc. So in case of this ADC this is the clock. But the sampling rate is significantly slower.
The sampling rate consists of multiple components.
1. Sampling time. This is dependent also on source and multiplexer impedance. It is basically the time required to charge the internal sampling capacitor good enough for the required accuracy.
2. Conversion time. This is the time derived from the required clock cycles to perform the conversion of the sampled voltage on the internal sampling capacitor to the digital value.
3. Storing the result in memory.
4. Triggering the interrupt.

With all this under best conditions and the 5MHz clock, the ADC in this device can achieve 200ksps. You can find more details on this in the device User's Guide. www.ti.com/.../slau208q.pdf

Best regards
Peter