MSP430F5172: Sync of Timer D0 and Timer D1

I am sorry for the confusion. I want both timers to behave identically in up/down mode. The slave seems only to operate in up mode.

Thanks for your quick response.

Kevin 

Hi Kevin

I have test the msp430f5172 on my side and I found that is works well. Just one things that the TD1.2 out put is a little delayed as the picture.

And this is the Saleae capture file

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/166/25-MHz_2C00_-125-M-Samples-_5B00_8_5D00_.logicdata

This is my test code 

/* --COPYRIGHT--,BSD_EX
 * Copyright (c) 2012, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************
 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//*******************************************************************************
//  MSP430F51x2 Demo - TimerD0, PWM TD0.1-2, Up/Down Mode, DCO SMCLK
//
//  Description: This program generates two PWM outputs on P1.7 and P2.0 using
//  TimerD0 configured for up/down mode. The value in CCR0, 128, defines the
//  PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using
//  ~1.045MHz SMCLK as TDCLK, the timer period is ~233us with a 75% duty cycle
//  on P1.7 and 25% on P2.0. PWM freq = 4kHz. 
//  SMCLK = MCLK = TDCLK = default DCO ~1.045MHz.
//
//                MSP430F51x2
//            -------------------
//        /|\|                   |
//         | |                   |
//         --|RST                |
//           |                   |
//           |         P1.7/TD0.1|--> CCR1 - 75% PWM
//           |         P2.0/TD0.2|--> CCR2 - 25% PWM
//
//  B. Nisarga
//  Texas Instruments Inc.
//  Dec 2009
//  Built with CCS v4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  // configure ports
  P1SEL |= BIT7;                            // P1.7, option select
  P1DIR |= BIT7;                            // P1.7 output
  P2SEL |= BIT2;                            // P2.0 options select
  P2DIR |= BIT2;                            // P2.0 output
  
  // Configure TD0
  TD0CCR0 = 128;                            // PWM Period/2
  TD0CCTL1 = OUTMOD_6;                      // CCR1 toggle/set
  TD0CCR1 = 96;                             // CCR2 PWM duty cycle
  TD0CTL0 = TDSSEL_2 + MC_3 + TDCLR;        // SMCLK, up-down mode, clear TDR

  // Configure TD0
  TD1CCR0 = 128;                            // PWM Period/2
  TD1CCTL1 = OUTMOD_6;                      // CCR1 toggle/set
  TD1CCR1 = 96;                             // CCR2 PWM duty cycle
  TD1CTL0 = TDSSEL_2 + MC_3 + TDCLR;        // SMCLK, up-down mode, clear TDR*/

  __bis_SR_register(LPM0_bits);             // Enter LPM0
  __no_operation();                         // For debugger
}

I don't know the reason but if you don't want that delay you can just use TD0 and defferent CCR channels that will generate more than two PWM out put with no delayed.

 Best regards

Gary

Hi Gary,

Thanks for your response. However it is not the problem I am having. Once again I apologize for not being clear, I hope the following sheds more light on my problem.

I need 4 synchronized phases as this is a dynamically controlled push-pull power supply with synchronized rectifiers. I went with the timer D due to its much higher resolution and therefore finer control.  As you know the timer D in this device only has 3 modules in 2 timers.  For the most part and for sure in this application module 0 is of little value as an output. My design relied on the following information found in the MSP430x5xx and MSP430x6xx Users guide (slauq.pdf). 

from page 531 Timer D operation

19.2.10 Synchronization Between Timer_D Instances
For some devices that contain more than one Timer_D instance, internal signals assist the
synchronization between different timers. Those signals include Timer Clock, TDAUXCLK,
TDAUXCLROUT, and some other signals that connect the Timer_D module and the Timer Event Control
module. See the TEC chapter for details

from page 552 TEC operation

20.2.5 Synchronization Mechanism Between Timer_D Instances
Two or more Timer_D modules can be synchronized to each other. One instance can be the master of the
other Timer_D instance (slave). The master is the instance that supplies the clock to the other instance. If
two timer instances are synchronized to each other, then there is a device specific order; for example,
Timer0_D is the master of Timer1_D. The slave uses the settings of the TDHEN bit, the CNTLx bits, and
the MCx bits of the master. The CCR0 registers of the master and the slave must be programmed to
equal values. Figure 20-5 shows the combination of a Timer_D master and a Timer_D slave and the
control signals routed through the TEC module of the slave. The clock generator of the Timer_D slave is
powered down by selecting the TDCLKMx to accept the clock input from the Timer_D master. The
TECEXCLR signals of the slave timers do not propagate to the master but the clear events of the master
timers are signaled to the slave timers. See Figure Figure 20-5 for the detailed signal routing between
master and slave. The divider and clock selector settings of the slave timers are ignored. The high
resolution generator of the slave timer is disabled.
The Example 20-1 shows how to program the master timer and the slave timer to synchronize them.

As I read this it clearly states that the MC bits are carried from the master to the slave. The code example given uses the MC_1 which is up mode. This does work I have run it. The problem is I need the phase relationship that can only be generated by the up/down mode MC_3. When I use the exact same code in MC_3 mode, the slave timer appears to remain in MC_1 mode. When the timers are put into synchronize mode the TDxCTL0 register of the slave is not populated. This implies to me that there is a different mechanism going on to create this synchronization. The proof I have that the slave remains in up mode  is that if  I stop the timers when TDIFG  bit is set is set I can see the count on the slave timer starting from zero whereas the master timer is counting down from the value loaded in the CCR0 register. The output of the slave timer also seems odd in that  the output is in sync with the master timer, but the pulse width is wider and only occurs 1/2 the time making it appear the frequency is 1/2 of the master.

The question is is there something else I must due to use the timers in the UP/DOWN mode or is the documentation wrong. My code is identical to that in example 20-1 of the TEC operation. The only difference is the TDxCCRx values, and MC_1 replace with MC_3

Hi Gary,

I appreciate that your trying to resolve the problem. I just don't think your understanding the problem. The code you wrote is not syncing the 2 timers together. Syncing the 2 timers together so there is no delay can be done I have done it in MC_1 mode as shown in the example code in the TEC module guide. What is implied is that the MC_3 mode can also be used and synced together but appears not to.

So to start can you find out if , when the timers are synced together as described in the TEC module is it possible that they will operate correctly in MC_3 mode.

I can not  use your methodology because it is critical that the 2 timers remain in sync as I change PWM pulse width and frequency which can not be done as in your example.

What you need to do is copy the code in the TEC module for syncing the 2 timers, and then change MC_1 to MC_3 in the example and you will see the issue.  If the module will not work in MC_3 mode then so be it, but the documentation should reflect that (see my earlier reply ) as I had highlighted.

Kevin

Hi Gary,

That is interesting that the code in the TEC operation example 20-1 does not work well for you, and in my experience only works in MC_1 mode, and does not work in MC_3 mode. Apparently that whole section 20.2.5 of the user guide is wrong. I appreciate the effort on this issue and I will submit a request for documentation change. Unfortunately I will have to redesign the power supply based on this information.

Thanks 

Kevin

Hi Gary,

Once again it appears I am unclear. The example in 20.2.5  works fine in MC_1 mode which I had already stated, and you have now proven, I want to run it in MC_3 MODE.  Re-write the code in 20.2.5 replacing MC_1 with MC_3 then put a scope on the 4 signals, you will find that TD0_1 and TD0_2 will be at 2X the frequency of TD1_1 and TD1_2. I don't know how else to put it.

Regards 

Kevin