Other Parts Discussed in Thread: MSP430WARE, MSP430FR2355
Hi
I tried ADC repeated sequence of channels samples code shared by TI but it is not working properly. all it is doing that it is sampling one channels only and showing its result on all other channels instead of sampling all channels.
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//******************************************************************************
// MSP430FR235x Demo - ADC, Sample A2/A1/A0, internal 2V Ref.
//
// Description: This example works on Sequence-of-Channels Mode.
// A2/A1/A0 is sampled 16ADCclks with reference to 2V.
// Internal oscillator times sample (16x) and conversion(13x).
// Inside ADC_ISR A2/A1/A0 sample value put into array ADC_Result[3].
// ACLK = default REFO ~32768Hz, MCLK = SMCLK = default DCODIV ~1MHz.
//
//
// MSP430FR2355
// -----------------
// /|\| |
// | | |
// --|RST |
// | |
// >---|P1.2/A2 |
// >---|P1.1/A1 |
// >---|P1.0/A0 |
//
//
// Cash Hao
// Texas Instruments Inc.
// November 2016
// Built with IAR Embedded Workbench v6.50.0 & Code Composer Studio v6.2.0
//******************************************************************************
#include <msp430.h>
unsigned int ADC_Result[3]; // 12-bit ADC conversion result array
unsigned char i;
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// Configure ADC A1~2 pins
P1SEL0 |= BIT1 + BIT2;
P1SEL1 |= BIT1 + BIT2;
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
// Configure ADC
ADCCTL0 |= ADCSHT_2 | ADCMSC | ADCON; // 16ADCclks, MSC, ADC ON
ADCCTL1 |= ADCSHP | ADCCONSEQ_1 | ADCSSEL_1; // ADC clock ACLK, sampling timer, s/w trig.,single sequence
ADCCTL2 &= ~ADCRES; // clear ADCRES in ADCCTL
ADCCTL2 |= ADCRES_2; // 12-bit conversion results
ADCMCTL0 |= ADCINCH_2 | ADCSREF_1; // A0~2(EoS); Vref=2V
ADCIE |= ADCIE0; // Enable ADC conv complete interrupt
// Configure reference
PMMCTL0_H = PMMPW_H; // Unlock the PMM registers
PMMCTL2 |= INTREFEN | REFVSEL_1; // Enable internal 2V reference
__delay_cycles(400); // Delay for reference settling
__no_operation();
while(1)
{
i = 2;
while(ADCCTL1 & ADCBUSY); // Wait if ADC core is active
ADCCTL0 |= ADCENC | ADCSC; // Sampling and conversion start
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
__no_operation(); // Only for debug
__delay_cycles(5000);
__no_operation();
}
}
// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
{
case ADCIV_NONE:
break;
case ADCIV_ADCOVIFG:
break;
case ADCIV_ADCTOVIFG:
break;
case ADCIV_ADCHIIFG:
break;
case ADCIV_ADCLOIFG:
break;
case ADCIV_ADCINIFG:
break;
case ADCIV_ADCIFG:
ADC_Result[i] = ADCMEM0;
if(i == 0)
{
__bic_SR_register_on_exit(LPM0_bits); // Exist LPM0
}
else
{
i--;
}
break;
default:
break;
}
}
