Part Number: MSP432P401R
Hello,
I'm trying to build a 3 channel synchronized PWM DAC with a cycle by cycle update capability, and I thought that I could take advantage of the fact that there are two TimerAx triggers. The plan was to use the CCR0 trigger to update CCR1 in a 16 bit transfer, and then use the CCR2 trigger to update CCR3 and CCR4 using a 32 bit transfer.
However, when I try to do this on the MSP432, it appears that the CCR2 DMA trigger is simply not being triggered.
Here are some test scenarios I tried:
| DMA CH0 CCR0 EN | CH0 SRC INC | CH0 DEST | CH1CCR2 EN | CH1 SRC INC | CH1 DEST | Result |
| Y | 16 | TA0CCR1 | Y | 32 | TA0CCR3 | DMA updates to CCR1, no DMA updates to CCR3/4 |
| N | N/A | N/A | Y | 32 | TA0CCR3 | No DMA updates to CCR1, CCR3, or CCR4 |
| N | N/A | N/A | Y | 16 | TA0CCR3 | DMA updates to CCR3 |
| N | N/A | N/A | Y | 16 | TA0CCR4 | DMA updates to CCR4 |
| Y | 16 | TA0CCR1 | Y | 16 | TA0CCR3 | DMA updates to CCR1, CCR3. No updates on CCR4 |
I had DMA CH1 assigned to a seperate DMA_ISR handler, and as expected this never gets called because the transfer never completes.
Any thoughts on why a 32 bit transfer here is invalid? The timer CCRx memory space is contiguous so in theory it should work. Does the timer A peripheral truncate all writes to 16 bits?
Looking forward to some ideas.
Regards,
Munan
