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CCS/MSP430F5529: UCS

Part Number: MSP430F5529

Tool/software: Code Composer Studio

I don`t know what`s problem with my code ,I want to set the MSP430F2259 for a 100MHZ MCLK and SMCLK but it`s not work. Here is my code.

WDTCTL = WDTPW + WDTHOLD;
P2DIR = BIT2;
P2SEL = BIT2;

P5SEL |= BIT2+BIT3;

UCSCTL6 &= ~XT2OFF;
do
{
UCSCTL7 &= ~XT2OFFG;
}while (UCSCTL7&XT2OFFG);

UCSCTL3 |= SELREF_5;
UCSCTL4 |= SELA_2;
__delay_cycles(256000);
__bis_SR_register(SCG0);
UCSCTL0_H = 0xFF;
UCSCTL0_L = 0x00;
UCSCTL1 = DCORSEL_7;
UCSCTL2 = FLLD_1 + 24;
__bic_SR_register(SCG0);
do
{
UCSCTL7 &= ~(XT2OFFG+XT1LFOFFG+DCOFFG);
SFRIFG1 &= ~OFIFG;
}while(SFRIFG1&OFIFG);
UCSCTL4 &= ~SELS_4;
UCSCTL4 |= SELS_3;

  • Hello my engineering friend,

    Were you aware the maximum clock frequency for the MSP430F5529 is 25Mhz as stated in the datasheet, page 22?

  • sorry I forgot this , BUT how about the SMCLK , the frequency of SMCLK is 50MHZ using this code.

    And I also want to know , since the maximum frequency can only be 25MHZ, can the DC0 frequency reach 135MHZ be supplied to ACLK?

    What is the significance of the DCO frequency exceeding 25MHZ?

  • First I want to clarify that the 25MHz is a limitation for the CPU MCLK, not the DCO.  This means you should be able to run the DCO at higher frequencies but you will need to divide the clock down so it meets the 25MHz limitation.  Running the MCLK faster than 25MHz will probably exceed the internal switching speeds and the CPU will most likely stop working properly, especially across voltages and temperatures.

    Maybe you can explain why you want the DCO to run at higher frequency.

    Just to make you aware, SMCLK is also limited to 25MHz as is the clock frequency inputs to the TIMERS, USCI (SPI and UART) and the IO Port pins.

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