WEBENCH® Tools/MSP430F6779A: MSP430F6779A

Tool/software: WEBENCH® Design Tools

I am trying to measure count in a pulse from one rising edge to next rising edge for this purpose I am giving a 1Hz pulse externally to one of the pin of MCU. I have setup a timer and also did the port setting but I am unable to make a logic for counting the pulse. I have tried various logics but still not able to find the count. I am also attaching my code below. Ignore things I have declared but did not use in code.

#include "io430f6779a.h"

#define ENABLE_GIE    __bis_SR_register(GIE)

#define FLAG_stop 0
#define BIT_TRUE(A, B)      ((A) & (0x01<<(B)))

#define INPUT_PIN_STATUS          BIT_TRUE(P1OUT, 6)
#define OUTPUT_PIN_STATUS      BIT_TRUE(P1IN, 6)

unsigned int OFFcount,Total, off_set,count,CNT;
unsigned char Flag_Count;
char Flag_Stop;
unsigned char read;
unsigned char Stat;
unsigned int High1[2],Low1[2];
unsigned int old_off_set;

void Clock_Init() ;
int main(void)
{

WDTCTL = WDTPW | WDTHOLD; // Stop WDT
Clock_Init() ; // clock intiallization
ENABLE_GIE;

P1IE |= BIT6 ; //Port1 interrupt enable
P1SEL0 &=~ BIT6; //bit selection
P1DIR &= ~BIT6; //Bit direction
P1IN &= ~BIT6;



P1IES &= ~(BIT6); // EDGE SELCTION LOW TO HIGH
// P2IES |= BIT2; // EDGE SELECTION HIGH TO LOW



TA0CCTL0= CCIE; // Capture/compare interrupt enable
TA0CCR0 = 1050; // 1ms sec
TA0CCTL1 = OUTMOD_7; //controls TA via external connection
TA0CTL = TASSEL_2 | TACLR | MC_1 ; // SMCLK, up mode
TA0EX0 = TAIDEX_7; // divider

unsigned long Low, High;
Flag_Count =1;
while(1)
{
WDTCTL = WDT_ARST_1000; //clear watchdog

if(Flag_Count == 1)
{
if(BIT_TRUE(P1IN, 6))
{
High++;
}
else
{
Low++;
}
}
// Flag_Count =0;

}
}

// Timer Overflow Interrupt
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void) //8ms
{
// CNT++;
// OFFcount++;
// if(OFFcount>999)
if(off_set)
{
OFFcount++;
}
// old_off_set=off_set;
// if(TAIFG)
// {
// Flag_Stop=1;
// OFFcount++;
// // Total++;
// // P1OUT ^=BIT6;
// }
// else if
// {
// OFFcount=0;
//
// }
}

//Port 2 Interrupt
#pragma vector = PORT1_VECTOR
__interrupt void InterruptVectorPort1()
{
off_set++;
P1IFG &= ~(BIT6);
}

//Clock Initialli
void Clock_Init()
{
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 |= SELREF__XT1CLK; // Set DCO FLL reference = REFO
// PMMCTL0_H=PMMPW_H;
// PMMCTL0_L|=PMMCOREV_3;
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
} while (UCSCTL7 & XT1LFOFFG); // Test XT1 fault flag


// UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_6; // Select DCO range 16MHz operation

UCSCTL2 = FLLD_0 | 510; // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
UCSCTL6 = XT1DRIVE_1; // (243 + 1) * 32768 = 8MHz
// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
// Loop until XT1, XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
}