• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 79 subscribers
  • Views 363 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP432P401R: configuring BSL interface issue

Ying Rui Sebestian Tan
Prodigy 125 points

Part Number: MSP432P401R

Hi,

Currently, my client is having a problem with MSP432P401R configuring BSL interface issue. 

The following is the BSL config in the flash mailbox:

    /* BSL Starting address, default pointing to TI BSL at 0x00202000 */

    BSL_API_TABLE_ADDR,

 

   /* BSL Parameter

     * Use HW Invoke on Port 1, Pin 1, on HIGH

     * Use UART

     */

    BSL_CONFIG_HW_INVOKE_PORT1 | BSL_CONFIG_HW_INVOKE_PIN5 |

    BSL_CONFIG_HW_INVOKE | BSL_CONFIG_HW_INVOKE_PIN_HIGH |

    BSL_CONFIG_INTERFACE_UART,

 

And I'm controlling the reset and P1.5 with my beagle bone black and getting the following traces on the system

Chan 1 / Yellow = P1.5

Chan 2 / Green = TX

Chan 3 / Blue = Reset

Chan 4 / Red = RX

The following images are the same sequence but at different time scales.

 

The dip on the TX is the sync byte (0x80) but there is not the expected response to it.

Any advice?

Sebestian 

Field Applications Associate  

  • 0
    TI__Mastermind 22640 points

    Hello Sebestian,

    I will have to try this and check out. I can work on this on Monday.

    Thanks,

    Sai

  • 0
    TI__Mastermind 22640 points

    Hello Sebestian,

    According to the MSP432P4xx BSL User's Guide, section 3.3.2 Hardware BSL Invocation, it looks like the pin used to invoke BSL should be asserted for a few cycles after Reset is asserted. It's not clear how many cycles though...

    From the above image, the second arrow is when BSL gets executed, the first arrow is when the Bootcode gets executed. Can you increase the duration for which P1.5 is high to ensure that the BSL is actually invoked?

    Ying Rui Sebestian Tan said:
    The dip on the TX is the sync byte (0x80) but there is not the expected response to it.

    According to the MSP432P4xx BSL User's Guide, 2.2 UART Protocol Definition, the Sync word is 0xFF. Is there a reason you are using 0x80?

    Thanks,

    Sai

**Attention** This is a public forum